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參數資料
型號: PSD301V-70J
廠商: 意法半導體
英文描述: Low Cost Field Programmable Microcontroller Peripherals
中文描述: 低成本現場可編程微控制器外圍設備
文件頁數: 16/85頁
文件大小: 691K
代理商: PSD301V-70J
NOTES:
1. CSI is a power-down signal. When high, the PAD is in stand-by mode and all its outputs
become non-active. See Tables 12 and 13.
2. RESET deselects all PAD output signals. See Tables 10 and 11.
3. A18, A17, and A16 are internally multiplexed with CS10, CS9, and CS8, respectively.
Either A18 or CS10, A17 or CS9, and A16 or CS8 can be routed to the external pins of
Port C. Port C pins can be configured as either input or output, individually.
4. P
0
–P
3
are not included on 3X1 devices.
5. DS is not available on 3X1 devices.
Figure 4.
PADDescription
ALE or AS
WR or R/W
A19
A18
A17
A16
A15
A14
A13
A12
A11
ES0
ES1
ES2
ES3
ES4
ES5
ES6
ES7
RS0
CSIOPORT
CSADIN
CSADOUT1
CSADOUT2
CS0/PB0
CS1/PB1
CS2/PB2
CS3/PB3
CS4/PB4
CS5/PB5
CS6/PB6
CS7/PB7
CS8/PC0
CS9/PC1
CS10/PC2
RD/E/DS
8 EPROM BLOCK
SELECT LINES
CSI
RESET
SRAM BLOCK SELECT
*
TRACK MODE
CONTROL SIGNALS
P
0
P
1
P
2
P
3
I/O BASE ADDRESS
PAD
B
PAD
A
PSD3XX Famly
13
*
SRAM no available on “R” versions
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