- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376250 > PSD302-70JI (意法半導體) Low Cost Field Programmable Microcontroller Peripherals PDF資料下載
參數(shù)資料
| 型號： | PSD302-70JI |
| 廠商： | 意法半導體 |
| 英文描述： | Low Cost Field Programmable Microcontroller Peripherals |
| 中文描述： | 低成本現(xiàn)場可編程微控制器外圍設備 |
| 文件頁數(shù)： | 7/85頁 |
| 文件大小： | 691K |
| 代理商： | PSD302-70JI |
第1頁第2頁第3頁第4頁第5頁第6頁當前第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁
PSD3XX Famly
4
3.0
Key Features
J
Single-chip programmable peripheral for microcontroller-based applications
J
256K to 1 Mbit of UV EPROM with the following features:
Configurable as 32, 64, or 128 K x 8; or as 16, 32, or 64 K x 16
Divided into eight equally-sized mappable blocks for optimized address mapping
As fast as 70 ns access time, which includes address decoding
J
Optional 16 Kbit SRAM is configurable as 2K x 8 or 1K x 16. The access time can be
as quick as 70 ns, including address decoding.
J
19 I/O pins that can be individually configured for :
Microcontroller I/O port expansion
Programmable Address decoder (PAD) I/O
Latched address output
Open-drain or CMOS output
J
Two Programmable Arrays (PAD A and PAD B) replace your PLD or decoder, and have
the following features:
Up to 18 Inputs and 24 outputs
40 Product terms (13 for PAD A and 27 for PAD B)
Ability to decode up to 1 MB of address without paging
J
Microcontroller logic that eliminates the need for external “glue logic” has the following
features:
Ability to interface to multiplexed and non-multiplexed buses
Built-in address latches for multiplexed address/data bus
ALE and Reset polarity are programmable (Reset polarity not programmable on
V-versions)
Multiple configurations are possible for interface to many different microcontrollers
J
Optional built-in page logic expands the MCU address space by up to 16 times
J
Programmable power management with standby current as low as 1μA for low-voltage
version
CMiser bit—programmable option to reduce AC power consumption in memory
Turbo Bit (ZPSD only)—programmable bit to reduce AC and DC power consumption
in the PADs.
J
Track Mode that allows other microcontrollers or host processors to share access to the
local data bus
J
Built-in security locks the device and PAD decoding configuration
J
Wide Operating Voltage Range
V-versions: 2.7 to 5.5 volts
Others: 4.5 to 5.5 volts
J
Available in a variety of packaging (44-pin PLDCC, CLDCC, TQFP, and PQFP)
J
Simple, menu-driven software (PSDsoft) allows configuration and design entry on a PC.
相關PDF資料 |
PDF描述 |
|---|---|
| PSD302-70JM | Low Cost Field Programmable Microcontroller Peripherals |
| PSD302-90J | Low Cost Field Programmable Microcontroller Peripherals |
| PSD302-90JI | Low Cost Field Programmable Microcontroller Peripherals |
| PSD302-90JM | Low Cost Field Programmable Microcontroller Peripherals |
| PSD302-A-15J | Low Cost Field Programmable Microcontroller Peripherals |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PSD302-70JM | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Low Cost Field Programmable Microcontroller Peripherals |
| PSD302-70LI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD302-70LM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD302-70Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD302-70QI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
發(fā)布緊急采購，3分鐘左右您將得到回復。