- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376250 > PSD302-90JM (意法半導(dǎo)體) Low Cost Field Programmable Microcontroller Peripherals PDF資料下載
參數(shù)資料
| 型號： | PSD302-90JM |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Low Cost Field Programmable Microcontroller Peripherals |
| 中文描述： | 低成本現(xiàn)場可編程微控制器外圍設(shè)備 |
| 文件頁數(shù)： | 15/85頁 |
| 文件大小： | 691K |
| 代理商： | PSD302-90JM |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當(dāng)前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁
PSD3XX Famly
12
Multiplexed Address/Data
Non-Multiplexed Address/Data
8-bit Data Bus
I/O or low-order address
lines or Low-order multiplexed
address/data byte
Port A
D0–D7 data bus byte
Port B
I/O and/or CS0–CS7
I/O and/or CS0–CS7
AD0/A0–AD7/A7
Low-order multiplexed
address/data byte
Low-order address bus byte
AD8/A8–AD15/A15
High-order address
bus byte
High-order address bus byte
16-bit Data Bus
I/O or low-order address
lines or low-order multiplexed
address/data byte
Port A
Low-order data bus byte
Port B
I/O and/or CS0–CS7
High-order data bus byte
AD0/A0–AD7/A7
Low-order multiplexed
address/data byte
Low-order address bus byte
AD8/A8–AD15/A15
High-order multiplexed
address/data byte
High-order address bus byte
8.0
Operating
Modes (MCU
Configurations)
(cont.)
Table 3. Bus and Port Configuration Options
9.0
Programmable
Address
Decoder (PAD)
The PSD3XX contains two programmable arrays, referred to as PAD A and PAD B
(Figure 4). PAD A is used to generate chip select signals derived from the input address to
the internal EPROM blocks, SRAM, I/O ports, and Track Mode signals.
PAD B outputs to Ports B and C for off-chip usage. PAD B can also be used to extend the
decoding to select external devices or as a random logic replacement.
PAD A and PAD B receive the same inputs. The PAD logic is configured by PSDsoft
based on the designer’s input. The PAD’s non-volatile configuration is stored in a
re-programmable CMOS EPROM. Windowed packages are available for erasure by the
user. See Table 4 for a list of PAD A and PAD B functions.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD302-A-15J | Low Cost Field Programmable Microcontroller Peripherals |
| PSD302-A-15JI | Low Cost Field Programmable Microcontroller Peripherals |
| PSD302-A-15JM | Low Cost Field Programmable Microcontroller Peripherals |
| PSD302-A-20J | Low Cost Field Programmable Microcontroller Peripherals |
| PSD302-A-20JI | Low Cost Field Programmable Microcontroller Peripherals |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD302-90LI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD302-90LM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD302-90Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD302-90QI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD302-90U | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。