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參數資料
| 型號： | PSD303-B-90UI |
| 廠商： | 意法半導體 |
| 英文描述： | Low Cost Field Programmable Microcontroller Peripherals |
| 中文描述： | 低成本現場可編程微控制器外圍設備 |
| 文件頁數： | 24/85頁 |
| 文件大小： | 691K |
| 代理商： | PSD303-B-90UI |
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PSD3XX Famly
21
11.
PSDMemory
The following sections explain the various memory blocks and memory options within the
PSD3XX.
11.1 EPROM
For all of the PSD3XX devices, the EPROM is built using Zero-power technology. This
means that the EPROM powers up only when the address changes. It consumes power for
the necessary time to latch data on its outputs. After this, it powers down and remains in
Standby Mode until the next address change. This happens automatically, and the designer
has to do nothing special.
The EPROM is divided into eight equal-sized banks. Each bank can be placed in any
address location by programming the PAD. Bank0-Bank7 are selected by PAD A outputs
ES0-ES7, respectively. There is one product term for each bank select (ESi).
Refer to Table 1 to see the size of the EPROM for each PSD device.
11.2 SRAM (Optional)
Like the EPROM, the optional SRAM in the PSD3XX devices is built using Zero-power
technology.
All PSD3XX parts which do not have an R suffix contain 2 Kbytes of SRAM (Table 1). The
SRAM is selected by the RS0 output of the PAD. There is one product term dedicated to
RS0.
If your design requires a SRAM larger than 2K x 8, then use one of the RAMless
(R versions) of the 3XX devices with an external SRAM. The external SRAM can be
addressed trhough Port A and all require logic will be taken care of by the PSD3XXR.
11.3 Page Register (Optional)
All PSD3XX parts, except 3X1devices, have a four-bit page register. Thus the effective
address space of your MCU can be enlarged by a factor of 16. Each bit of the Page
Register can be individually read or written. The Page Register is located in CSIOPORT
space (at offset 18h); see Table 5. The Page Register is connected to the lowest nibble of
the data bus (D3-D0). The outputs of the Page Register, P3-P0, are connected to PAD A,
and therefor can be used in any chip select (internal or external) equations. The contents of
the page register are reset to zero at power-up and after any chip-level reset.
11.4 Programmng and Erasure
Programming the device can be done using the following methods:
ST
’s main programmer—PSDpro—which is accessible through a parallel port.
ST
’s programmer used specifically with the PSD3XX—PEP300.
ST
’s discontinued programmer—Magic Pro.
A 3rd party programmer, such as Data I/O.
Information for programming the device is available directly from
ST
. Please contact your
local sales representative. Also, check our web site (
www.st
.com
/psm
) for information related
to 3rd party programmers.
Upon delivery from
ST
or after each erasure (using windowed part), the PSD3XX device
has all bits in PAD and EPROM in the HI state (logic 1). The configuration bits are in the LO
state (logic 0).
To clear all locations of their programmed contents (assuming you have a windowed
version), expose the windowed device to an Ultra-Violet (UV) light source. A dosage of
30 W second/cm
2
is required for PSD3XX devices, and 40 W second/cm
2
for low-voltage
(V suffix) devices. This dosage can be obtained with exposure to a wavelength of 2537
and intensity of 12000 μW/cm
2
for 40 to 45 minutes for the PSD3XX and 55 to 60 minutes
for the low-voltage (V suffix) devices. The device should be approximately 1 inch (2.54 cm)
from the source, and all filters should be removed from the UV light source prior to erasure.
The PSD3XX devices will erase with light sources having wavelengths shorter than 4000 .
However, the erasure times will be much longer than when using the recommended 2537
wavelength. Note: exposure to sunlight will eventually erase the device. If used in such an
environment, the package window should be covered with an opaque substance.
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