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參數資料
| 型號： | PSD312-70J |
| 廠商： | 意法半導體 |
| 英文描述： | High Speed PWM Controller 16-PDIP 0 to 70 |
| 中文描述： | 低成本現場可編程微控制器外圍設備 |
| 文件頁數： | 36/85頁 |
| 文件大小： | 691K |
| 代理商： | PSD312-70J |
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PSD3XX Famly
33
All the inputs shown, except CSI, go to the PAD logic. These signals must be taken into
consideration when calculating the composite frequency. Before we make the calculation,
let’s establish the following conditions:
The input with the highest frequency is ALE, which is 2 MHz. So our base period is
500 nsec for this example.
Only the address information from the multiplexed signals AD0-AD7 reach the PAD
logic because of the internal address latch. Signal transitions from data on AD0-AD7
do not reach the PADs.
The three inputs (Int, Sel, or Rdy) change state very infrequently relative to the 80C31
bus signals.
Now, lets assume the following is a snapshot in time of all the input signals during a typical
80C31 bus cycle. We’ll use a code fetch as an example since that happens most often.
16.0
Power
Management
(cont.)
ONE TYPICAL 80C31 BUS CYCLE (2 MHz, 500 nsec)
ALE
PSEN
AD0-AD7
A8-A15
INT
SEL
RDY
FOUR DISTINCT
TRANSITIONS
<25 nsec
ADDR
DATA
1
2
3
The calculation of the composite frequency is as follows:
There are four distinct transitions (first four dotted lines) within the base period of
500 nsec. These first four transitions all count toward the final composite frequency.
The transition at (1) in the diagram does not count as a distinct transition because it is
within 25 nsec of a neighboring transition (use 50 nsec for a ZPSD3XXV device).
Transition (2) above does not add to the composite frequency because only the
internally latched address signals reach the PADs, the data signal transitions do not.
The transition at (3) just happens to appear in this snapshot, but its frequency is so
low that it is not a significant contributor to the overall composite frequency, and will
not be used.
Divide the 500 nsec base period by the four (distinct transitions), yielding 125 nsec.
1/125 nsec = 8 MHz.
Use 8 MHz as the composite frequency of PAD inputs when calculating current
consumption. (See the next section for a sample current calculation.)
16.6 Loading on I/Opins
A final consideration when calculating the current usage for the entire PSD device is the
loading on I/O pins. All specifications for PSD current consumption in this document
assume zero current flowing through PSD I/O pins (including ADIO). I/O current is dictated
by the individual design implementation, and must be calculated by the designer. Be aware
that I/O current is a function of loading on the pins and the frequency at which the signals
toggle.
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PDF描述 |
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| PSD312-70JI | Low Cost Field Programmable Microcontroller Peripherals |
| PSD312-70JM | High Speed PWM Controller 20-PLCC 0 to 70 |
| PSD312-90J | Low Cost Field Programmable Microcontroller Peripherals |
| PSD312-90JI | High Speed PWM Controller 16-SOIC 0 to 70 |
| PSD312-90JM | Low Cost Field Programmable Microcontroller Peripherals |
相關代理商/技術參數 |
參數描述 |
|---|---|
| PSD312-70JI | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Low Cost Field Programmable Microcontroller Peripherals |
| PSD312-70JM | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Low Cost Field Programmable Microcontroller Peripherals |
| PSD312-70LI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD312-70LM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD312-70Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
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