- 您現在的位置：買賣IC網 > PDF目錄376251 > PSD312V-A-90JM (意法半導體) Low Cost Field Programmable Microcontroller Peripherals PDF資料下載
參數資料
| 型號： | PSD312V-A-90JM |
| 廠商： | 意法半導體 |
| 英文描述： | Low Cost Field Programmable Microcontroller Peripherals |
| 中文描述： | 低成本現場可編程微控制器外圍設備 |
| 文件頁數： | 21/85頁 |
| 文件大小： | 691K |
| 代理商： | PSD312V-A-90JM |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁
PSD3XX Famly
18
10.
I/OPort
Functions
(
cont.)
10.3 Port B (PB0-PB7)
The control registers of Port B are located in CSIOPORT space; see Table 5A and 5B.
10.3.1 Port B (PB0-PB7) in Multiplexed Address/Data Mode
Each pin of Port B can be individually configured. The following table summarizes what the
control registers (in CSIOPORT space) for Port B do:
NOTE:
1. Default value is the value after reset.
Default
Value
(Note 1)
Register Name
0 Value
1 Value
Port B Pin Register
Sampled logic level
at pin = ‘0’
Pin is configured
as input
Data in DFF = ‘0’
Sampled logic level
at pin = ‘1’
Pin is configured
as output
Data in DFF = ‘1’
X
Port B Direction Register
0
Port B Data Register
0
MCUI/OMode
The default configuration of Port B is MCU I/O. In this mode, every pin can be set
(at run-time) as an input or output by writing to the respective pin’s direction flip-flop (DIR
FF, Figure 6). As an output, the pin level can be controlled by writing to the respective pin’s
data flip-flop (DFF, Figure 6). The Pin Register can be read to determine logic level of the
pin. The contents of the Pin Register indicate the true state of the PSD driving the pin
through the DFF or an external source driving the pin. Pins can be configured as CMOS
or open-drain using
ST
’s PSDsoft software. Open-drain pins require external pull-up
resistors.
Chip Select Output
Alternatively, each bit of Port B can be configured to provide a chip-select output signal
from PAD B. PB0-PB7 can provide CS0-CS7, respectively. The functionality of these pins is
not limited to chip selects only; they can be used for generic combinatorial logic as well.
Each of the CS0-CS3 signals is comprised of four product terms, and each of the CS4-CS7
signals is comprised of two product terms.
相關PDF資料 |
PDF描述 |
|---|---|
| PSD313-15J | Current-Mode PWM Controller 8-PDIP 0 to 70 |
| PSD313-15JI | Current-Mode PWM Controller 8-PDIP 0 to 70 |
| PSD313-15JM | Low Cost Field Programmable Microcontroller Peripherals |
| PSD313-20J | Current Mode PWM Controller 14-SOIC 0 to 70 |
| PSD313-20JI | Current Mode PWM Controller 8-SOIC 0 to 70 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| PSD313-12J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD313-12JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD313-12LI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD313-12LM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD313-12Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
發布緊急采購，3分鐘左右您將得到回復。