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參數(shù)資料
| 型號： | PSD413A2 |
| 英文描述： | Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個可編程I/O,通用PLD有59個輸入) |
| 中文描述： | 現(xiàn)場可編程微控制器外圍設(shè)備（可編程邏輯，16K的位的SRAM，40余個可編程輸入/輸出，通用PLD的有59個輸入） |
| 文件頁數(shù)： | 1/97頁 |
| 文件大小： | 309K |
| 代理商： | PSD413A2 |
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4-1
Key Features
Programmable Peripheral
PSD4XX Famly
Field-Programmable Microcontroller Peripherals
J
Complete family of Field Programmable Microcontroller Peripherals enables the
user to efficiently implement a highly integrated embedded control system in a short
time. The PSD4XX family has a variety of functions such as ZPLDs , I/O Ports, Power
Management, EPROM and SRAM.
J
“No Glue-Logic” user programmable interface to 8 or 16 bit microcontroller multiplexed
and non-multiplexed bus. The bus control logic can directly decode control signals
generated by 8031, 80196, 80186, 68HC11, 68HC16, 683XX, 16000, Z80, and Z8
architecture. Extended address capability up to 24 bits of address.
J
A range of ZPLD (Zero Power PLD) architectures have up to 24 macrocells, 59 inputs
and 126 output product terms. The PSD4XX includes 2 functional ZPLDs which enable
the user to efficiently implement a variety of state machines, logic functions, address
decoding and control of the internal PSD4XX functional blocks .
J
The ZPLDs use a Zero Power CMOS technology that reduces the device standby
current to 10 μA typical. Unused product terms are disabled to reduce operating power.
J
40 I/O Ports that can be individually configured by the user as standard MCU I/O ports,
PLD I/O, latched address outputs and special function I/O. Two eight bit I/O ports can
be configured as Open Drain Outputs.
J
The PSD4XX family contains EPROM densities of 256 Kbit, 512 Kbit and 1 Mbit that
can be configured as 8 or 16 bit data width. The EPROM is divided into 4 equal blocks
that can be mapped to different address spaces. Access time is 70 ns which includes
address latching and decoding PLD. The EPROM has a low power mode that is
controlled by the CMiser-Bit.
J
The PSD4XX family contains a 16 Kbit scratch pad SRAM that can be configured
as 8 or 16 bit data width. Access time is 70 ns which includes address latching and
decoding PLD. The SRAM can be used as standby storage if standby power is supplied
to the Vstdby pin. Switching between V
CC
and Vstdby occurs automatically.
J
Page Logic is connected to the ZPLDs and enables address space expansion of
Microcontrollers with limited address space capability. Up to 16 pages are available.
J
A security bit prevents reading the PSD4XX configuration, ZPLD and EPROM contents.
This inhibits copying the device on a programmer.
J
Port A can be used as a buffered microcontroller data bus ( Peripheral I/O Mode) of the
microcontroller bus. This provides easy access to sub-systems that require more drive
on the data bus or accessing a resource that is shared by another MCU or DMA
Controller.
J
PSD4XX standard versions are ideal for general purpose applications
J
PSD4XXM mask-programmable versions are ideal for code-stable, high-volume low
cost applications
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD4135G2(中文) | Flash In-System-Programmable Peripherals for 16-Bit MCUs(用于16位MCU的閃速在系統(tǒng)可編程外圍芯片) |
| PSD4135G2 | Flash In-System-Programmable Peripherals for 16-Bit MCUs(用于16位MCU的閃速在系統(tǒng)可編程外圍芯片) |
| PSD4135G2 | 100V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a Low Ohmic TO-257AA package. Also available with 300kRad Total Dose Rating.; A IRHYS67130CM with Standard Packaging |
| PSD4135G2V | 130V 100kRad Hi-Rel Single N-Channel SEE Hardened MOSFET in a TO-254AA package; IRHMS57163SE JANS Certified Part Number |
| PSD4135F1-70B81 | LCD Display Panel; No. of Digits/Alpha:64; Display Technology:LCD; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD413A2-C-70L | 制造商:WSI 功能描述: |
| PSD4-16 | 制造商:Tamura Corporation of America 功能描述: |
| PSD4-20 | 制造商:MICROTRAN 功能描述:POWER TRANSFORMER, 6 VA |
| PSD4235G2-70U | 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 4M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD4235G2-90U | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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