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參數資料
型號: PSD4256G6V
廠商: 意法半導體
英文描述: FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERALS FOR 16-BIT MCUS
中文描述: Flash在系統編程(ISP)外設的16位微控制器
文件頁數: 1/100頁
文件大小: 759K
代理商: PSD4256G6V
1/100
PRELIMINARY DATA
December 2002
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PSD4256G6V
Flash In-System Programmable (ISP)
Peripherals for 16-bit MCUs
FEATURES SUMMARY
PSD provides an integrated solution to 16-bit
MCU-based applications that includes config-
urable memories, PLD logic, and I/O:
I
Dual bank Flash memories
– 8Mbits of Primary Flash Memory (16 uniform
sectors, 64Kbyte)
– 512Kbits of Secondary Flash Memory with 4
sectors
– Concurrent operation: READ from one mem-
ory while erasing and writing the other
I
256Kbits of SRAM (battery-backed)
I
PLD with Macrocells
– Over 3000 Gates of PLD: CPLD and DPLD
– CPLD with 16 Output Macrocells (OMCs) and
24 Input Macrocells (IMCs)
– DPLD - user defined internal chip select de-
coding
I
Seven l/O Ports with 52 I/O pins:
52 individually configurable I/O port pins that
can be used for the following functions:
– MCU I/Os
– PLD I/Os
– Latched MCU address output
– Special function I/Os
– l/O ports may be configured as open-drain
outputs
I
In-System Programming (ISP) with JTAG
– Built-in JTAG compliant serial port allows full-
chip In-System Programmability
– Efficient manufacturing allow easy product
testing and programming
– Use low cost FlashLINK cable with PC
I
Page Register
– Internal page register that can be used to ex-
pand the microcontroller address space by a
factor of 256
I
Programmable power management
I
High Endurance:
– 100,000 Erase/WRITE Cycles of Flash Mem-
ory
– 1,000 Erase/WRITE Cycles of PLD
– 15 Year Data Retention
I
Single Supply Voltage
– 3V (+20%/–10%)
I
Memory Speed
– 100ns Flash memory and SRAM access time
for V
CC
= 3V (+20%/–10%)
– 90ns Flash memory and SRAM access time
for V
CC
= 3.3V (+/–10%)
Figure 1. 80-lead, Thin, Quad, Flat Package
TQFP80 (U)
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相關代理商/技術參數
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PSD4256G6V-10UI 功能描述:CPLD - 復雜可編程邏輯器件 3.3V 8M 100ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD4-36 制造商:Tamura Corporation of America 功能描述:
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