欧美成人免费电影,国产欧美一区二区三区精品酒店,精品国产a毛片,色网在线免费观看

參數(shù)資料
型號： PSD8133V90JIT
廠商： 意法半導體
英文描述： Flash In-System Programmable ISP Peripherals For 8-bit MCUs
中文描述： Flash在系統(tǒng)可編程ISP的外設的8位微控制器
文件頁數(shù)： 64/110頁
文件大小： 1737K
代理商： PSD8133V90JIT
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
64/110
For Users of the HC11 (or compatible)
The HC11 turns off its E clock when it sleeps.
Therefore, if you are using an HC11 (or compati-
ble) in your design, and you wish to use the Pow-
er-down mode, you must not connect the E clock
to CLKIN (PD1). You should instead connect a
crystal oscillator to CLKIN (PD1). The crystal oscil-
lator frequency must be
less than
15 times the fre-
quency of AS. The reason for this is that if the
frequency is greater than 15 times the frequency
of AS, the PSD keeps going into Power-down
mode.
Other Power Saving Options
The PSD offers other reduced power saving op-
tions that are independent of the Power-down
mode. Except for the SRAM Stand-by and PSD
Chip Select Input (CSI, PD2) features, they are en-
abled by setting bits in PMMR0 and PMMR2.
Figure 33. Enable Power-down Flow Chart
PLD Power Management
The power and speed of the PLDs are controlled
by the Turbo Bit (Bit 3) in PMMR0. By setting the
bit to '1,' the Turbo mode is off and the PLDs con-
sume the specified stand-by current when the in-
puts are not switching for an extended time of
70ns. The propagation delay time is increased by
10ns after the Turbo Bit is set to '1' (turned off)
when the inputs change at a composite frequency
of less than 15 MHz. When the Turbo Bit is reset
to '0' (turned on), the PLDs run at full power and
speed. The Turbo Bit affects the PLD’s DC power,
AC power, and propagation delay.
Blocking MCU control signals with the bits of
PMMR2 can further reduce PLD AC power con-
sumption.
SRAM Standby Mode (Battery Backup).
The
PSD supports a battery backup mode in which the
contents of the SRAM are retained in the event of
a power loss. The SRAM has Voltage Stand-by
(V
STBY
, PC2) that can be connected to an external
battery. When V
CC
becomes lower than V
STBY
then the PSD automatically connects to Voltage
Stand-by (V
STBY
, PC2) as a power source to the
SRAM. The SRAM Standby Current (I
STBY
) is typ-
ically 0.5μA. The SRAM data retention voltage is
2V minimum. The Battery-on Indicator (VBATON)
can be routed to PC4. This signal indicates when
the V
CC
has dropped below V
STBY
.
Enable APD
Set PMMR0 Bit 1 = 1
PSD in Power
Down Mode
ALE/AS idle
for 15 CLKIN
clocks
RESET
Yes
No
OPTIONAL
Disable desired inputs to PLD
by setting PMMR0 bits 4 and 5
and PMMR2 bits 2 through 6.
AI02892
相關(guān)PDF資料
PDF描述
PSD9133V90JIT Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD8333V90JIT Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD9333V90JIT Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD8533V90JIT Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD9533V90JIT Flash In-System Programmable ISP Peripherals For 8-bit MCUs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD8133V90JT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD8133V90MIT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD8133V90MT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD813412JIT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD813412JT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*
主站蜘蛛池模板： 法库县| 高密市| 宝丰县| 寿阳县| 炉霍县| 扶绥县| 宁强县| 公安县| 锡林郭勒盟| 兴义市| 芜湖县| 皋兰县| 凉城县| 嘉义县| 项城市| 宽城| 安图县| 宁明县| 麻栗坡县| 肇东市| 万年县| 青阳县| 壤塘县| 江源县| 景德镇市| 安溪县| 罗山县| 吉木萨尔县| 镇原县| 忻州市| 东城区| 孙吴县| 英超| 安平县| 藁城市| 治多县| 佛教| 青田县| 锡林浩特市| 清镇市| 恩平市|