- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376265 > PSD8145V20JT (意法半導(dǎo)體) Flash In-System Programmable ISP Peripherals For 8-bit MCUs PDF資料下載
參數(shù)資料
| 型號： | PSD8145V20JT |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| 中文描述： | Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器 |
| 文件頁數(shù)： | 28/110頁 |
| 文件大小： | 1737K |
| 代理商： | PSD8145V20JT |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁當(dāng)前第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
28/110
SPECIFIC FEATURES
Flash Memory Sector Protect
Each primary and secondary Flash memory sector
can be separately protected against Program and
Erase cycles. Sector Protection provides addition-
al data security because it disables all Program or
Erase cycles. This mode can be activated through
the JTAG Port or a Device Programmer.
Sector protection can be selected for each sector
using the PSDsoft Express Configuration pro-
gram. This automatically protects selected sectors
when the device is programmed through the JTAG
Port or a Device Programmer. Flash memory sec-
tors can be unprotected to allow updating of their
contents using the JTAG Port or a Device Pro-
grammer. The MCU can read (but cannot change)
the sector protection bits.
Any attempt to program or erase a protected Flash
memory sector is ignored by the device. The Verify
operation results in a READ of the protected data.
This allows a guarantee of the retention of the Pro-
tection status.
The sector protection status can be read by the
MCU through the Flash memory protection and
PSD/EE protection registers (in the CSIOP block).
See Tables
11
and
12
.
Reset Flash
The Reset Flash instruction consists of one
WRITE cycle (see
Table 9., page 21
). It can also
be optionally preceded by the standard two
WRITE decoding cycles (writing AAh to 555h and
55h to AAAh). It must be executed after:
–
Reading the Flash Protection Status or Flash
ID
–
An Error condition has occurred (and the
device has set the Error Flag Bit (DQ5) to '1')
during a Flash memory Program or Erase
cycle.
On the PSD813F2/3/4/5, the Reset Flash instruc-
tion puts the Flash memory back into normal
READ Mode. It may take the Flash memory up to
a few milliseconds to complete the Reset cycle.
The Reset Flash instruction is ignored when it is is-
sued during a Program or Bulk Erase cycle of the
Flash memory. The Reset Flash instruction aborts
any on-going Sector Erase cycle, and returns the
Flash memory to the normal READ Mode within a
few milliseconds.
On the PSD83xF2 or PSD85xF2, the Reset Flash
instruction puts the Flash memory back into nor-
mal READ Mode. If an Error condition has oc-
curred (and the device has set the Error Flag Bit
(DQ5) to '1') the Flash memory is put back into nor-
mal READ Mode within 25
μ
s of the Reset Flash in-
struction having been issued. The Reset Flash
instruction is ignored when it is issued during a
Program or Bulk Erase cycle of the Flash memory.
The Reset Flash instruction aborts any on-going
Sector Erase cycle, and returns the Flash memory
to the normal READ Mode within 25
μ
s.
Reset (RESET) Signal (on the PSD83xF2 and
PSD85xF2)
A pulse on Reset (RESET) aborts any cycle that is
in progress, and resets the Flash memory to the
READ Mode. When the reset occurs during a Pro-
gram or Erase cycle, the Flash memory takes up
to 25
μ
s to return to the READ Mode. It is recom-
mended that the Reset (RESET) pulse (except for
Power On Reset, as described on
RESET TIMING
AND DEVICE STATUS AT RESET, page 67
) be
at least 25
μ
s so that the Flash memory is always
ready for the MCU to fetch the bootstrap instruc-
tions after the Reset cycle is complete.
Table 11. Sector Protection/Security Bit Definition – Flash Protection Register
Note: 1. Bit Definitions:
Sec<i>_Prot
1 = Primary Flash memory or secondary Flash memory Sector <i> is write protected.
Sec<i>_Prot
0 = Primary Flash memory or secondary Flash memory Sector <i> is not write protected.
Table 12. Sector Protection/Security Bit Definition – PSD/EE Protection Register
Note: 1. Bit Definitions:
Sec<i>_Prot
1 = Secondary Flash memory Sector <i> is write protected.
Sec<i>_Prot
0 = Secondary Flash memory Sector <i> is not write protected.
Security_Bit
0 = Security Bit in device has not been set.
1 = Security Bit in device has been set.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Sec7_Prot
Sec6_Prot
Sec5_Prot
Sec4_Prot
Sec3_Prot
Sec2_Prot
Sec1_Prot
Sec0_Prot
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Security_Bit
not used
not used
not used
Sec3_Prot
Sec2_Prot
Sec1_Prot
Sec0_Prot
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD8145V20MIT | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD8145V20MT | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD8145V70MIT | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD813412JIT | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD813415JIT | Fast Transient Response 5 Ampere Low Dropout (LDO) Regulator 5-DDPAK/TO-263 0 to 70 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD833F2-90J | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD833F2-90JI | 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD833F2-90M | 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD833F2-90MI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD834F2-15M | 制造商:STMicroelectronics 功能描述:Flash In-System Programmable Peripherals 52-Pin PQFP |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。