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參數(shù)資料
型號(hào): PSD833270JIT
廠商: 意法半導(dǎo)體
英文描述: Flash In-System Programmable ISP Peripherals For 8-bit MCUs
中文描述: Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
文件頁(yè)數(shù): 12/110頁(yè)
文件大小: 1737K
代理商: PSD833270JIT
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
12/110
PC2
18
I/O
PC2 pin of Port C. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellBC2) output.
Input to the PLDs.
V
STBY
– SRAM stand-by voltage input for SRAM battery backup.
This pin can be configured as a CMOS or Open Drain output.
PC3
17
I/O
PC3 pin of Port C. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellBC3) output.
Input to the PLDs.
TSTAT output
2
for the JTAG Serial Interface.
Ready/Busy output for parallel In-System Programming (ISP).
This pin can be configured as a CMOS or Open Drain output.
PC4
14
I/O
PC4 pin of Port C. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellBC4) output.
Input to the PLDs.
TERR output
2
for the JTAG Serial Interface.
Battery-on Indicator (V
BATON
). Goes High when power is being drawn from the external
battery.
This pin can be configured as a CMOS or Open Drain output.
PC5
13
I/O
PC5 pin of Port C. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellBC5) output.
Input to the PLDs.
TDI input
2
for the JTAG Serial Interface.
This pin can be configured as a CMOS or Open Drain output.
PC6
12
I/O
PC6 pin of Port C. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellBC6) output.
Input to the PLDs.
TDO output
2
for the JTAG Serial Interface.
This pin can be configured as a CMOS or Open Drain output.
Pin Name
Pin
Type
Description
相關(guān)PDF資料
PDF描述
PSD833270JT High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125
PSD833270MIT High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125
PSD833270MT High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125
PSD833290MT High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125
PSD8332V12JT High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD833F2-90J 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD833F2-90JI 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD833F2-90M 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD833F2-90MI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD834F2-15M 制造商:STMicroelectronics 功能描述:Flash In-System Programmable Peripherals 52-Pin PQFP
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