欧美成人免费电影,国产欧美一区二区三区精品酒店,精品国产a毛片,色网在线免费观看

參數資料
型號: PSD834F3-70
廠商: 意法半導體
英文描述: RECTIFIER SCHOTTKY SINGLE 5A 40V 175A-Ifsm 0.55Vf 0.5A-IR SMC 3K/REEL
中文描述: Flash在系統可編程(ISP)的周邊8位MCU,5V的
文件頁數: 36/110頁
文件大小: 1737K
代理商: PSD834F3-70
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
36/110
Complex PLD (CPLD)
The CPLD can be used to implement system logic
functions, such as loadable counters and shift reg-
isters, system mailboxes, handshaking protocols,
state machines, and random logic. The CPLD can
also be used to generate three External Chip Se-
lect (ECS0-ECS2), routed to Port D.
Although External Chip Select (ECS0-ECS2) can
be produced by any Output Macrocell (OMC),
these three External Chip Select (ECS0-ECS2) on
Port D do not consume any Output Macrocells
(OMC).
As shown in
Figure 13., page 34
, the CPLD has
the following blocks:
24 Input Macrocells (IMC)
16 Output Macrocells (OMC)
Macrocell Allocator
Product Term Allocator
AND Array capable of generating up to 137
product terms
Four I/O Ports.
Each of the blocks are described in the sections
that follow.
The Input Macrocells (IMC) and Output Macrocells
(OMC) are connected to the PSD internal data bus
and can be directly accessed by the MCU. This
enables the MCU software to load data into the
Output Macrocells (OMC) or read data from both
the Input and Output Macrocells (IMC and OMC).
This feature allows efficient implementation of sys-
tem logic and eliminates the need to connect the
data bus to the AND Array as required in most
standard PLD macrocell architectures.
Figure 15. Macrocell and I/O Port
I/O PORTS
CPLD MACROCELLS
INPUT MACROCELLS
LATCHED
ADDRESS OUT
MUX
M
M
M
M
D
D
Q
Q
Q
G
D
Q D
WR
WR
PDR
DATA
PALLOCATOR
DIR
SELECT
INPUT
PFROM OTHER
MACROCELLS
POLARITY
PROUP TO 10
CLOCK
PR
DI LD
D/T
CK
CL
Q
SELECT
PT CLEAR
PT
GLOBAL
PT OUTPUT ENABLE (OE)
MACROCELL FEEDBACK
I/O PORT INPUT
ALE/AS
PT INPUT LATCH GATE/CLOCK
MCU LOAD
PT PRESET
MCU DATA IN
/REG
SELECT
MACTO
IALLOC.
OCPLD
TO OTHER I/O PORTS
P
P
MCU ADDRESS/DATA BUS
MOUT TO
MCU
CDATA
A
CPLD OUTPUT
I/O PIN
AI02874
相關PDF資料
PDF描述
PSD854F3-70 Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
PSD813F3-12 Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
PSD813F3-15 Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
PSD813F4-20 Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
PSD813F4-70 Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
相關代理商/技術參數
參數描述
PSD835G2-70U 功能描述:靜態隨機存取存儲器 5.0V 4M 70ns RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
PSD835G2-90U 功能描述:靜態隨機存取存儲器 5.0V 4M 90ns RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
PSD835G2-90UI 功能描述:靜態隨機存取存儲器 5.0V 4M 90ns RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
PSD835G2V-12UI 功能描述:靜態隨機存取存儲器 3.0V 4M 120ns RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
PSD835G2V-90U 功能描述:靜態隨機存取存儲器 3.0V 4M 90ns RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
主站蜘蛛池模板: 晴隆县| 全州县| 木里| 延津县| 阿拉善左旗| 五指山市| 阳西县| 潮州市| 舒兰市| 依安县| 蒲城县| 三都| 米泉市| 新巴尔虎左旗| 淮滨县| 平安县| 抚松县| 满洲里市| 邻水| 石河子市| 永新县| 平湖市| 磐安县| 金门县| 泸州市| 华蓥市| 尼勒克县| 贞丰县| 花垣县| 万安县| 溧阳市| 西青区| 尼勒克县| 湖南省| 铁岭市| 泾源县| 东平县| 调兵山市| 澄迈县| 铁岭县| 南乐县|