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參數資料
| 型號： | PSD853315MIT |
| 廠商： | 意法半導體 |
| 英文描述： | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| 中文描述： | Flash在系統可編程ISP的外設的8位微控制器 |
| 文件頁數： | 22/110頁 |
| 文件大小： | 1737K |
| 代理商： | PSD853315MIT |
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
22/110
INSTRUCTIONS
An instruction consists of a sequence of specific
operations. Each received byte is sequentially de-
coded by the PSD and not executed as a standard
WRITE operation. The instruction is executed
when the correct number of bytes are properly re-
ceived and the time between two consecutive
bytes is shorter than the time-out period. Some in-
structions are structured to include READ opera-
tions after the initial WRITE operations.
The instruction must be followed exactly. Any in-
valid combination of instruction bytes or time-out
between two consecutive bytes while addressing
Flash memory resets the device logic into READ
Mode (Flash memory is read like a ROM device).
The PSD supports the instructions summarized in
Table 9., page 21
:
Flash memory:
Erase memory by chip or sector
Suspend or resume sector erase
Program a Byte
Reset to READ Mode
Read primary Flash Identifier value
Read Sector Protection Status
Bypass (on the PSD833F2, PSD834F2,
PSD853F2 and PSD854F2)
These
instructions
are
9., page 21
. For efficient decoding of the instruc-
tions, the first two bytes of an instruction are the
coded cycles and are followed by an instruction
byte or confirmation byte. The coded cycles con-
sist of writing the data AAh to address X555h dur-
ing the first cycle and data 55h to address XAAAh
during the second cycle. Address signals A15-A12
are Don’t Care during the instruction WRITE cy-
cles. However, the appropriate Sector Select
(FS0-FS7 or CSBOOT0-CSBOOT3) must be se-
lected.
The primary and secondary Flash memories have
the same instruction set (except for Read Primary
Flash Identifier). The Sector Select signals deter-
mine which Flash memory is to receive and exe-
cute the instruction. The primary Flash memory is
selected if any one of Sector Select (FS0-FS7) is
High, and the secondary Flash memory is selected
if any one of Sector Select (CSBOOT0-
CSBOOT3) is High.
Power-up Mode
The PSD internal logic is reset upon Power-up to
the READ Mode. Sector Select (FS0-FS7 and
CSBOOT0-CSBOOT3) must be held Low, and
Write Strobe (WR, CNTL0) High, during Power-up
■
■
■
■
■
■
■
detailed
in
Table
for maximum security of the data contents and to
remove the possibility of a byte being written on
the first edge of Write Strobe (WR, CNTL0). Any
WRITE cycle initiation is locked when V
CC
is be-
low V
LKO
.
READ
Under typical conditions, the MCU may read the
primary Flash memory or the secondary Flash
memory using READ operations just as it would a
ROM or RAM device. Alternately, the MCU may
use READ operations to obtain status information
about a Program or Erase cycle that is currently in
progress. Lastly, the MCU may use instructions to
read special data from these memory blocks. The
following sections describe these READ functions.
Read Memory Contents
Primary Flash memory and secondary Flash
memory are placed in the READ Mode after Pow-
er-up, chip reset, or a Reset Flash instruction (see
Table 9., page 21
). The MCU can read the memo-
ry contents of the primary Flash memory or the
secondary Flash memory by using READ opera-
tions any time the READ operation is not part of an
instruction.
Read Primary Flash Identifier
The primary Flash memory identifier is read with
an instruction composed of 4 operations: 3 specific
WRITE operations and a READ operation (see
Ta-
ble 9., page 21
). During the READ operation, ad-
dress bits A6, A1, and A0 must be '0,0,1,'
respectively, and the appropriate Sector Select
(FS0-FS7) must be High. The identifier for the
PSD813F2/3/4/5 is E4h, and for the PSD83xF2 or
PSD85xF2 it is E7h.
Read Memory Sector Protection Status
The primary Flash memory Sector Protection Sta-
tus is read with an instruction composed of 4 oper-
ations: 3 specific WRITE operations and a READ
operation (see
Table 9., page 21
). During the
READ operation, address Bits A6, A1, and A0
must be '0,1,0,' respectively, while Sector Select
(FS0-FS7 or CSBOOT0-CSBOOT3) designates
the Flash memory sector whose protection has to
be verified. The READ operation produces 01h if
the Flash memory sector is protected, or 00h if the
sector is not protected.
The sector protection status for all NVM blocks
(primary Flash memory or secondary Flash mem-
ory) can also be read by the MCU accessing the
Flash Protection registers in PSD I/O space. See
the section entitled
Flash Memory Sector
Protect, page 28
for register definitions.
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| PSD853315MT | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
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| PSD853415MIT | 120V Boot, 3-A Peak, High Frequency, High-Side/Low-Side Driver 8-VSON -40 to 140 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| PSD853F2-70J | 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 1M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD853F2-70M | 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 1M 70ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD853F2-90J | 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD853F2-90JI | 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD853F2-90M | 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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