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參數資料
| 型號： | PSD853320JIT |
| 廠商： | 意法半導體 |
| 英文描述： | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| 中文描述： | Flash在系統可編程ISP的外設的8位微控制器 |
| 文件頁數： | 27/110頁 |
| 文件大小： | 1737K |
| 代理商： | PSD853320JIT |
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
ERASING FLASH MEMORY
Flash Bulk Erase
The Flash Bulk Erase instruction uses six WRITE
operations followed by a READ operation of the
status register, as described in
Table 9., page 21
.
If any byte of the Bulk Erase instruction is wrong,
the Bulk Erase instruction aborts and the device is
reset to the Read Flash memory status.
During a Bulk Erase, the memory status may be
checked by reading the Error Flag Bit (DQ5), the
Toggle Flag Bit (DQ6), and the Data Polling Flag
Bit (DQ7), as detailed in the section entitled
PRO-
GRAMMING FLASH MEMORY, page 25
. The Er-
ror Flag Bit (DQ5) returns a '1' if there has been an
Erase Failure (maximum number of Erase cycles
have been executed).
It is not necessary to program the memory with
00h because the PSD automatically does this be-
fore erasing to 0FFh.
During execution of the Bulk Erase instruction, the
Flash memory does not accept any instructions.
Flash Sector Erase
The Sector Erase instruction uses six WRITE op-
erations, as described in
Table 9., page 21
. Addi-
tional Flash Sector Erase codes and Flash
memory sector addresses can be written subse-
quently to erase other Flash memory sectors in
parallel, without further coded cycles, if the addi-
tional bytes are transmitted in a shorter time than
the time-out period of about 100μs. The input of a
new Sector Erase code restarts the time-out peri-
od.
The status of the internal timer can be monitored
through the level of the Erase Time-out Flag Bit
(DQ3). If the Erase Time-out Flag Bit (DQ3) is ’0,’
the Sector Erase instruction has been received
and the time-out period is counting. If the Erase
Time-out Flag Bit (DQ3) is '1,' the time-out period
has expired and the PSD is busy erasing the Flash
memory sector(s). Before and during Erase time-
out, any instruction other than Suspend Sector
Erase and Resume Sector Erase instructions
abort the cycle that is currently in progress, and re-
set the device to READ Mode. It is not necessary
to program the Flash memory sector with 00h as
the PSD does this automatically before erasing
(byte = FFh).
During a Sector Erase, the memory status may be
checked by reading the Error Flag Bit (DQ5), the
Toggle Flag Bit (DQ6), and the Data Polling Flag
Bit (DQ7), as detailed in the section entitled
PRO-
GRAMMING FLASH MEMORY, page 25
.
During execution of the Erase cycle, the Flash
memory accepts only Reset and Suspend Sector
Erase instructions. Erasure of one Flash memory
sector may be suspended, in order to read data
from another Flash memory sector, and then re-
sumed.
Suspend Sector Erase
When a Sector Erase cycle is in progress, the Sus-
pend Sector Erase instruction can be used to sus-
pend the cycle by writing 0B0h to any address
when an appropriate Sector Select (FS0-FS7 or
CSBOOT0-CSBOOT3) is High. (See
Table
9., page 21
). This allows reading of data from an-
other Flash memory sector after the Erase cycle
has been suspended. Suspend Sector Erase is
accepted only during an Erase cycle and defaults
to READ Mode. A Suspend Sector Erase instruc-
tion executed during an Erase time-out period, in
addition to suspending the Erase cycle, terminates
the time out period.
The Toggle Flag Bit (DQ6) stops toggling when the
PSD internal logic is suspended. The status of this
bit must be monitored at an address within the
Flash memory sector being erased. The Toggle
Flag Bit (DQ6) stops toggling between 0.1μs and
15μs after the Suspend Sector Erase instruction
has been executed. The PSD is then automatically
set to READ Mode.
If an Suspend Sector Erase instruction was exe-
cuted, the following rules apply:
–
Attempting to read from a Flash memory
sector that was being erased outputs invalid
data.
–
Reading from a Flash sector that was
not
being erased is valid.
–
The Flash memory
cannot
be programmed,
and only responds to Resume Sector Erase
and Reset Flash instructions (READ is an
operation and is allowed).
–
If a Reset Flash instruction is received, data in
the Flash memory sector that was being
erased is invalid.
Resume Sector Erase
If a Suspend Sector Erase instruction was previ-
ously executed, the erase cycle may be resumed
with this instruction. The Resume Sector Erase in-
struction consists of writing 030h to any address
while an appropriate Sector Select (FS0-FS7 or
CSBOOT0-CSBOOT3) is High. (See
Table
9., page 21
.)
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相關代理商/技術參數 |
參數描述 |
|---|---|
| PSD853F2-70J | 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 1M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD853F2-70M | 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 1M 70ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD853F2-90J | 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD853F2-90JI | 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD853F2-90M | 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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