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參數資料
型號： PSD853F3-20
廠商： 意法半導體
英文描述： Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
中文描述： Flash在系統可編程（ISP）的周邊8位MCU，5V的
文件頁數： 21/110頁
文件大小： 1737K
代理商： PSD853F3-20
21/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Table 9. Instructions
Note: 1. All bus cycles are WRITE bus cycles, except the ones with the “READ” label
2. All values are in hexadecimal:
X = Don’t Care. Addresses of the form XXXXh, in this table, must be even addresses
RA = Address of the memory location to be read
RD = Data read from location RA during the READ cycle
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of Write Strobe (WR, CNTL0).
PA is an even address for PSD in word programming mode.
PD = Data word to be programmed at location PA. Data is latched on the rising edge of Write Strobe (WR, CNTL0)
SA = Address of the sector to be erased or verified. The Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) of the sector to be
erased, or verified, must be Active (High).
3. Sector Select (FS0 to FS7 or CSBOOT0 to CSBOOT3) signals are active High, and are defined in PSDsoft Express.
4. Only address bits A11-A0 are used in instruction decoding.
5. No Unlock or instruction cycles are required when the device is in the READ Mode
6. The Reset instruction is required to return to the READ Mode after reading the Flash ID, or after reading the Sector Protection Sta-
tus, or if the Error Flag Bit (DQ5/DQ13) goes High.
7. Additional sectors to be erased must be written at the end of the Sector Erase instruction within 80μs.
8. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active, and
(A1,A0)=(1,0)
9. The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction.
10. The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in the Unlock Bypass
mode.
11. The system may perform READ and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protection Status
when in the Suspend Sector Erase mode. The Suspend Sector Erase instruction is valid only during a Sector Erase cycle.
12. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode.
13. The MCU cannot invoke these instructions while executing code from the same Flash memory as that for which the instruction is
intended. The MCU must fetch, for example, the code from the secondary Flash memory when reading the Sector Protection Status
of the primary Flash memory.
Instruction
FS0-FS7 or
CSBOOT0-
CSBOOT3
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Cycle 6
Cycle 7
READ
5
1
“READ”
RD @ RA
Read Main
Flash ID
6
1
AAh@
X555h
55h@
XAAAh
90h@
X555h
Read identifier
(A6,A1,A0 = 0,0,1)
Read Sector
Protection
6,8,13
1
AAh@
X555h
55h@
XAAAh
90h@
X555h
Read identifier
(A6,A1,A0 = 0,1,0)
Program a
Flash Byte
13
1
AAh@
X555h
55h@
XAAAh
A0h@
X555h
PD@ PA
Flash Sector
Erase
7,13
1
AAh@
X555h
55h@
XAAAh
80h@
X555h
AAh@ X555h
55h@
XAAAh
30h@
SA
30h
7
@
next SA
Flash Bulk
Erase
13
1
AAh@
X555h
55h@
XAAAh
80h@
X555h
AAh@ X555h
55h@
XAAAh
10h@
X555h
Suspend
Sector Erase
11
1
B0h@
XXXXh
Resume
Sector Erase
12
1
30h@
XXXXh
Reset
6
1
F0h@
XXXXh
Unlock Bypass
1
AAh@
X555h
55h@
XAAAh
20h@
X555h
Unlock Bypass
Program
9
1
A0h@
XXXXh
PD@ PA
Unlock Bypass
Reset
10
1
90h@
XXXXh
00h@
XXXXh
相關PDF資料
PDF描述
PSD853F3-70 Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
PSD853F3-90 Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
PSD853F3V-12 Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
PSD853F3V-15 Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
PSD853F3V-20 Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
相關代理商/技術參數
參數描述
PSD854F2-15J 制造商:STMicroelectronics 功能描述:4556DIE2HR - Trays
PSD854F2-70J 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 2M 70ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD854F2-70M 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 2M 70ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD854F2-90J 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD854F2-90JI 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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