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參數資料
| 型號： | PSD854F2-12JIT |
| 廠商： | 意法半導體 |
| 英文描述： | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| 中文描述： | Flash在系統可編程ISP的外設的8位微控制器 |
| 文件頁數： | 24/110頁 |
| 文件大小： | 1737K |
| 代理商： | PSD854F2-12JIT |
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
24/110
Data Polling Flag (DQ7)
When erasing or programming in Flash memory,
the Data Polling Flag Bit (DQ7) outputs the com-
plement of the bit being entered for programming/
writing on the DQ7 Bit. Once the Program instruc-
tion or the WRITE operation is completed, the true
logic value is read on the Data Polling Flag Bit
(DQ7, in a READ operation).
–
Data Polling is effective after the fourth WRITE
pulse (for a Program instruction) or after the
sixth WRITE pulse (for an Erase instruction). It
must be performed at the address being
programmed or at an address within the Flash
memory sector being erased.
–
During an Erase cycle, the Data Polling Flag
Bit (DQ7) outputs a ’0.’ After completion of the
cycle, the Data Polling Flag Bit (DQ7) outputs
the last bit programmed (it is a '1' after
erasing).
–
If the byte to be programmed is in a protected
Flash memory sector, the instruction is
ignored.
–
If all the Flash memory sectors to be erased
are protected, the Data Polling Flag Bit (DQ7)
is reset to '0' for about 100μs, and then returns
to the previous addressed byte. No erasure is
performed.
Toggle Flag (DQ6)
The PSD offers another way for determining when
the Flash memory Program cycle is completed.
During the internal WRITE operation and when ei-
ther the FS0-FS7 or CSBOOT0-CSBOOT3 is true,
the Toggle Flag Bit (DQ6) toggles from '0' to '1' and
'1' to '0' on subsequent attempts to read any byte
of the memory.
When the internal cycle is complete, the toggling
stops and the data read on the Data Bus D0-D7 is
the addressed memory byte. The device is now
accessible for a new READ or WRITE operation.
The cycle is finished when two successive READs
yield the same output data.
–
The Toggle Flag Bit (DQ6) is effective after the
fourth WRITE pulse (for a Program instruction)
or after the sixth WRITE pulse (for an Erase
instruction).
If the byte to be programmed belongs to a
protected Flash memory sector, the
instruction is ignored.
If all the Flash memory sectors selected for
erasure are protected, the Toggle Flag Bit
(DQ6) toggles to '0' for about 100μs and then
returns to the previous addressed byte.
Error Flag (DQ5)
During a normal Program or Erase cycle, the Error
Flag Bit (DQ5) is to ’0.’ This bit is set to '1' when
there is a failure during Flash memory Byte Pro-
gram, Sector Erase, or Bulk Erase cycle.
In the case of Flash memory programming, the Er-
ror Flag Bit (DQ5) indicates the attempt to program
a Flash memory bit from the programmed state,
’0,’ to the erased state, '1,' which is not valid. The
Error Flag Bit (DQ5) may also indicate a Time-out
condition while attempting to program a byte.
In case of an error in a Flash memory Sector Erase
or Byte Program cycle, the Flash memory sector in
which the error occurred or to which the pro-
grammed byte belongs must no longer be used.
Other Flash memory sectors may still be used.
The Error Flag Bit (DQ5) is reset after a Reset
Flash instruction.
Erase Time-out Flag (DQ3)
The Erase Time-out Flag Bit (DQ3) reflects the
time-out period allowed between two consecutive
Sector Erase instructions. The Erase Time-out
Flag Bit (DQ3) is reset to '0' after a Sector Erase
cycle for a time period of 100μs + 20% unless an
additional Sector Erase instruction is decoded. Af-
ter this time period, or when the additional Sector
Erase instruction is decoded, the Erase Time-out
Flag Bit (DQ3) is set to '1.'
–
–
相關PDF資料 |
PDF描述 |
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| PSD834F2-12JT | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD854F2-12JT | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD834F2-12M | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD834F2-12J | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD854F2-12J | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
相關代理商/技術參數 |
參數描述 |
|---|---|
| PSD854F2-15J | 制造商:STMicroelectronics 功能描述:4556DIE2HR - Trays |
| PSD854F2-70J | 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 2M 70ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD854F2-70M | 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 2M 70ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD854F2-90J | 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD854F2-90JI | 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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