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參數資料
型號: PSD854F4-20
廠商: 意法半導體
英文描述: Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
中文描述: Flash在系統可編程(ISP)的周邊8位MCU,5V的
文件頁數: 60/110頁
文件大小: 1737K
代理商: PSD854F4-20
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
60/110
Port D – Functionality and Structure
Port D has three I/O pins. See Figure
30
and
Fig-
ure 31., page 61
. This port does not support Ad-
dress Out mode, and therefore no Control
Register is required. Port D can be configured to
perform one or more of the following functions:
MCU I/O Mode
CPLD Output – External Chip Select (ECS0-
ECS2)
CPLD Input – direct input to the CPLD, no
Input Macrocells (IMC)
Slew rate – pins can be set up for fast slew
rate
Port D pins can be configured in PSDsoft Express
as input pins for other dedicated functions:
Address Strobe (ALE/AS, PD0)
CLKIN (PD1) as input to the macrocells flip-
flops and APD counter
PSD Chip Select Input (CSI, PD2). Driving this
signal High disables the Flash memory, SRAM
and CSIOP.
Figure 30. Port D Structure
I
DREG.
D
Q
D
Q
WR
WR
ECS[2:0]
READ MUX
P
D
B
CPLD-INPUT
DIR REG.
DATA IN
ENABLE PRODUCT
TERM (.OE)
SELECT
OMUX
PORT D PIN
DATA OUT
AI02889
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