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參數(shù)資料
型號： PSD854F4-70
廠商： 意法半導(dǎo)體
英文描述： Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
中文描述： Flash在系統(tǒng)可編程（ISP）的周邊8位MCU，5V的
文件頁數(shù)： 91/110頁
文件大?。?/td> 1737K
代理商： PSD854F4-70
91/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Table 57. WRITE Timing (5V devices)
Note: 1. Any input used to select an internal PSD function.
2. In multiplexed mode, latched address generated from ADIO delay to address output on any port.
3. WR has the same timing as E, LDS, UDS, WRL, and WRH signals.
4. Assuming data is stable before active WRITE signal.
5. Assuming WRITE is active before data becomes valid.
6. TWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory.
Symbol
Parameter
Conditions
-70
-90
-15
Unit
Min
Max
Min
Max
Min
Max
t
LVLX
ALE or AS Pulse Width
15
20
28
ns
t
AVLX
Address Setup Time
(Note
1
)
4
6
10
ns
t
LXAX
Address Hold Time
(Note
1
)
7
8
11
ns
t
AVWL
Address Valid to Leading
Edge of WR
(Notes
1,3
)
8
15
20
ns
t
SLWL
CS Valid to Leading Edge of WR
(Note
3
)
12
15
20
ns
t
DVWH
WR Data Setup Time
(Note
3
)
25
35
45
ns
t
WHDX
WR Data Hold Time
(Note
3
)
4
5
5
ns
t
WLWH
WR Pulse Width
(Note
3
)
31
35
45
ns
t
WHAX1
Trailing Edge of WR to Address Invalid
(Note
3
)
6
8
10
ns
t
WHAX2
Trailing Edge of WR to DPLD Address
Invalid
(Note
3,6
)
0
0
0
ns
t
WHPV
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
(Note
3
)
27
30
38
ns
t
DVMV
Data Valid to Port Output Valid
Using Macrocell Register
Preset/Clear
(Notes
3,5
)
42
55
65
ns
t
AVPV
Address Input Valid to Address
Output Delay
(Note
2
)
20
25
30
ns
t
WLMV
WR Valid to Port Output Valid Using
Macrocell Register Preset/Clear
(Notes
3,4
)
48
55
65
ns
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