- 您現在的位置：買賣IC網 > PDF目錄376293 > PSD854F5-12 (意法半導體) Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V PDF資料下載
參數資料
| 型號： | PSD854F5-12 |
| 廠商： | 意法半導體 |
| 英文描述： | Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V |
| 中文描述： | Flash在系統可編程（ISP）的周邊8位MCU，5V的 |
| 文件頁數： | 70/110頁 |
| 文件大?。?/td> | 1737K |
| 代理商： | PSD854F5-12 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁當前第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
70/110
JTAG Extensions
TSTAT and TERR are two JTAG extension signals
enabled by an “ISC_ENABLE” command received
over the four standard JTAG signals (TMS, TCK,
TDI, and TDO). They are used to speed Program
and Erase cycles by indicating status on PSD sig-
nals instead of having to scan the status out seri-
ally using the standard JTAG channel. See
Application Note
AN1153
.
TERR indicates if an error has occurred when
erasing a sector or programming a byte in Flash
memory. This signal goes Low (active) when an
Error condition occurs, and stays Low until an
“ISC_CLEAR” command is executed or a chip Re-
set (RESET) pulse is received after an
“ISC_DISABLE” command.
TSTAT behaves the same as Ready/Busy de-
scribed in the section entitled
Ready/Busy
(PC3), page 20
. TSTAT is High when the PSD de-
vice is in READ Mode (primary and secondary
Flash memory contents can be read). TSTAT is
Low when Flash memory Program or Erase cycles
are in progress, and also when data is being writ-
ten to the secondary Flash memory.
TSTAT and TERR can be configured as open-
drain type signals during an “ISC_ENABLE” com-
mand. This facilitates a wired-OR connection of
TSTAT signals from multiple PSD devices and a
wired-OR connection of TERR signals from those
same devices. This is useful when several PSD
devices are “chained” together in a JTAG environ-
ment.
Security and Flash memory Protection
When the security bit is set, the device cannot be
read on a Device Programmer or through the
JTAG Port. When using the JTAG Port, only a Full
Chip Erase command is allowed.
All other Program, Erase and Verify commands
are blocked. Full Chip Erase returns the part to a
non-secured blank state. The Security Bit can be
set in PSDsoft Express Configuration.
All primary and secondary Flash memory sectors
can individually be sector protected against era-
sures. The sector protect bits can be set in PSD-
soft Express Configuration.
Table 34. JTAG Port Signals
Port C Pin
JTAG Signals
Description
PC0
TMS
Mode Select
PC1
TCK
Clock
PC3
TSTAT
Status
PC4
TERR
Error Flag
PC5
TDI
Serial Data In
PC6
TDO
Serial Data Out
相關PDF資料 |
PDF描述 |
|---|---|
| PSD854F5-15 | Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V |
| PSD854F5-20 | Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V |
| PSD854F5-70 | Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V |
| PSD854F5-90 | Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V |
| PSD854F5V-12 | Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V |
相關代理商/技術參數 |
參數描述 |
|---|---|
| PSD-8M-01 | 制造商:Richco 功能描述:CB SPT REST MNT NAT 8MM SPC |
| PSD913212JIT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913212JT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913212MIT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913212MT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
發布緊急采購，3分鐘左右您將得到回復。