- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376274 > PSD913320MIT (意法半導(dǎo)體) BBG ECL TRNSLATR QUAD; Package: SOEIAJ-20; No of Pins: 20; Container: Tape and Reel; Qty per Container: 2000 PDF資料下載
參數(shù)資料
| 型號(hào)： | PSD913320MIT |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | BBG ECL TRNSLATR QUAD; Package: SOEIAJ-20; No of Pins: 20; Container: Tape and Reel; Qty per Container: 2000 |
| 中文描述： | Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器 |
| 文件頁(yè)數(shù)： | 19/110頁(yè) |
| 文件大小： | 1737K |
| 代理商： | PSD913320MIT |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)當(dāng)前第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)
19/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
DETAILED OPERATION
As shown in
Figure 5., page 14
, the PSD consists
of six major types of functional blocks:
Memory Blocks
PLD Blocks
MCU Bus Interface
I/O Ports
Power Management Unit (PMU)
JTAG Interface
The functions of each block are described in the
following sections. Many of the blocks perform
multiple functions, and are user configurable.
■
■
■
■
■
■
Memory Blocks
The PSD has the following memory blocks:
–
Primary Flash memory
–
Optional Secondary Flash memory
–
Optional SRAM
The Memory Select signals for these blocks origi-
nate from the Decode PLD (DPLD) and are user-
defined in PSDsoft Express.
Table 8. Memory Block Size and Organization
Primary Flash Memory
Secondary Flash Memory
SRAM
Sector
Number
Sector Size
(Bytes)
Sector Select
Signal
Sector Size
(Bytes)
Sector Select
Signal
SRAM Size
(Bytes)
SRAM Select
Signal
0
32K
FS0
16K
CSBOOT0
256K
RS0
1
32K
FS1
16K
CSBOOT1
2
32K
FS2
16K
CSBOOT2
3
32K
FS3
16K
CSBOOT3
4
32K
FS4
5
32K
FS5
6
32K
FS6
7
32K
FS7
Total
512K
8 Sectors
64K
4 Sectors
256K
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD913320MT | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913370JIT | TTL, NMOS To PECL Trans; Package: 20 LEAD PDIP; No of Pins: 20; Container: Rail; Qty per Container: 18 |
| PSD913370JT | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913370MIT | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913370MT | Quad CMOS to PECL Translator; Package: 20 LEAD PLLC; No of Pins: 20; Container: Rail; Qty per Container: 46 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD913320MT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913370JIT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913370JT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913370MIT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913370MT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。