欧美成人免费电影,国产欧美一区二区三区精品酒店,精品国产a毛片,色网在线免费观看

參數資料
型號: PSD913370JT
廠商: 意法半導體
英文描述: Flash In-System Programmable ISP Peripherals For 8-bit MCUs
中文描述: Flash在系統可編程ISP的外設的8位微控制器
文件頁數: 67/110頁
文件大小: 1737K
代理商: PSD913370JT
67/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
RESET TIMING AND DEVICE STATUS AT RESET
Power-Up Reset
Upon Power-up, the PSD requires a Reset (RE-
SET) pulse of duration t
NLNH-PO
after V
CC
is
steady. During this period, the device loads inter-
nal configurations, clears some of the registers
and sets the Flash memory into Operating mode.
After the rising edge of Reset (RESET), the PSD
remains in the Reset mode for an additional peri-
od, t
OPR
, before the first memory access is al-
lowed.
The Flash memory is reset to the READ Mode
upon Power-up. Sector Select (FS0-FS7 and
CSBOOT0-CSBOOT3) must all be Low, Write
Strobe (WR, CNTL0) High, during Power On Re-
set for maximum security of the data contents and
to remove the possibility of a byte being written on
the first edge of Write Strobe (WR, CNTL0). Any
Flash memory WRITE cycle initiation is prevented
automatically when V
CC
is below V
LKO
.
Warm Reset
Once the device is up and running, the device can
be reset with a pulse of a much shorter duration,
t
NLNH
.
The same t
OPR
period is needed before the device
is operational after warm reset. Figure
34
shows
the timing of the Power-up and warm reset.
I/O Pin, Register and PLD Status at Reset
Table 33., page 68
shows the I/O pin, register and
PLD status during Power On Reset, warm reset
and Power-down mode. PLD outputs are always
valid during warm reset, and they are valid in Pow-
er On Reset once the internal PSD Configuration
bits are loaded. This loading of PSD is completed
typically long before the V
CC
ramps up to operat-
ing level. Once the PLD is active, the state of the
outputs are determined by the PSDabel equa-
tions.
Reset of Flash Memory Erase and Program
Cycles (on the PSD834Fx)
A Reset (RESET) also resets the internal Flash
memory state machine. During a Flash memory
Program or Erase cycle, Reset (RESET) termi-
nates the cycle and returns the Flash memory to
the Read Mode within a period of t
NLNH-A
.
Figure 34. Reset (RESET) Timing
tNLNH-PO
Power-On Reset
tOPR
AI02866b
RESET
tNLNH
tNLNH-A
Warm Reset
tOPR
V
CC
V
CC
(min)
相關PDF資料
PDF描述
PSD913370MIT Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913370MT Quad CMOS to PECL Translator; Package: 20 LEAD PLLC; No of Pins: 20; Container: Rail; Qty per Container: 46
PSD913390JIT Quad CMOS to PECL Translator; Package: 20 LEAD PLLC; No of Pins: 20; Container: Tape and Reel; Qty per Container: 500
PSD913390JT Quad CMOS to PECL Translator; Package: 20 LEAD PLLC; No of Pins: 20; Container: Tape and Reel; Qty per Container: 500
PSD913390MIT Flash In-System Programmable ISP Peripherals For 8-bit MCUs
相關代理商/技術參數
參數描述
PSD913370MIT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913370MT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913390JIT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913390JT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913390MIT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
主站蜘蛛池模板: 尚志市| 拜城县| 志丹县| 聂荣县| 江西省| 金乡县| 静乐县| 陈巴尔虎旗| 睢宁县| 庆城县| 德阳市| 清水河县| 葫芦岛市| 富宁县| 东至县| 巴青县| 长海县| 浦县| 汪清县| 甘德县| 吉林市| 惠来县| 察哈| 蚌埠市| 肥城市| 西峡县| 梧州市| 延川县| 玛纳斯县| 萍乡市| 宁城县| 海阳市| 荥阳市| 荣成市| 巧家县| 虞城县| 平阳县| 长武县| 富民县| 汤原县| 通辽市|