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參數(shù)資料
型號(hào)： PSD913415MIT
廠商： 意法半導(dǎo)體
英文描述： BBG ECL TRNSLATR 9BIT; Package: 28 LEAD PLCC; No of Pins: 28; Container: Tape and Reel; Qty per Container: 500
中文描述： Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
文件頁(yè)數(shù)： 58/110頁(yè)
文件大?。?/td> 1737K
代理商： PSD913415MIT
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
58/110
Input Macrocells (IMC)
The Input Macrocells (IMC) can be used to latch or
store external inputs. The outputs of the Input
Macrocells (IMC) are routed to the PLD input bus,
and can be read by the MCU. See the section en-
titled
PLDS, page 33
.
Enable Out
The Enable Out register can be read by the MCU.
It contains the output enable values for a given
port. A 1 indicates the driver is in output mode. A
0 indicates the driver is in tri-state and the pin is in
input mode.
Ports A and B – Functionality and Structure
Ports A and B have similar functionality and struc-
ture, as shown in Figure
28
. The two ports can be
configured to perform one or more of the following
functions:
MCU I/O Mode
CPLD Output – Macrocells McellAB7-
McellAB0 can be connected to Port A or Port
B. McellBC7-McellBC0 can be connected to
Port B or Port C.
CPLD Input – Via the Input Macrocells (IMC).
Latched Address output – Provide latched
address output as per
Table 21., page 54
.
Address In – Additional high address inputs
using the Input Macrocells (IMC).
Open Drain/Slew Rate – pins PA3-PA0 and
PB3-PB0 can be configured to fast slew rate,
pins PA7-PA4 and PB7-PB4 can be
configured to Open Drain Mode.
Data Port – Port A to D7-D0 for 8 bit non-
multiplexed bus
Multiplexed Address/Data port for certain
types of MCU bus interfaces.
Peripheral Mode – Port A only
■
■
■
■
■
■
■
■
■
Figure 28. Port A and Port B Structure
I
DAREG.
D
Q
D
G
Q
D
Q
D
Q
WR
WR
WR
ADDRESS
MACROCELL OUTPUTS
ENABLE PRODUCT TERM (.OE)
ALE
READ MUX
P
D
B
CPLD-INPUT
CONTROL REG.
DIR REG.
INPUT
MACROCELL
ENABLE OUT
DATA IN
OUTPUT
OMUX
A PORT
DATA OUT
ADDRESS
A[7:0] OR A[15:8]
AI02887
相關(guān)PDF資料
PDF描述
PSD913415MT Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913420MIT BBG ECL TRNSLATR 9BIT; Package: 28 LEAD PLCC; No of Pins: 28; Container: Rail; Qty per Container: 37
PSD913420MT 9-Bit Latch/ECL-TTL Translator; Package: 28 LEAD PLCC; No of Pins: 28; Container: Tape and Reel; Qty per Container: 500
PSD913470JIT BBG ECL TRNSLATR 9BIT; Package: 28 LEAD PLCC; No of Pins: 28; Container: Tape and Reel; Qty per Container: 500
PSD913470JT Flash In-System Programmable ISP Peripherals For 8-bit MCUs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD913415MT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913420JIT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913420JT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913420MIT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913420MT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
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