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參數(shù)資料
型號(hào): PSD913420JT
廠商: 意法半導(dǎo)體
英文描述: Flash In-System Programmable ISP Peripherals For 8-bit MCUs
中文描述: Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
文件頁(yè)數(shù): 88/110頁(yè)
文件大小: 1737K
代理商: PSD913420JT
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
88/110
Table 55. READ Timing (5V devices)
Note: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals.
2. RD and PSEN have the same timing.
3. Any input used to select an internal PSD function.
4. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
5. RD timing has the same timing as DS, LDS, and UDS signals.
Symbol
Parameter
Conditions
-70
-90
-15
Turbo
Off
Unit
Min
Max
Min
Max
Min
Max
t
LVLX
ALE or AS Pulse Width
15
20
28
ns
t
AVLX
Address Setup Time
(Note
3
)
4
6
10
ns
t
LXAX
Address Hold Time
(Note
3
)
7
8
11
ns
t
AVQV
Address Valid to Data Valid
(Note
3
)
70
90
150
+ 10
ns
t
SLQV
CS Valid to Data Valid
75
100
150
ns
t
RLQV
RD to Data Valid 8-Bit Bus
(Note
5
)
24
32
40
ns
RD or PSEN to Data Valid
8-Bit Bus, 8031, 80251
(Note
2
)
31
38
45
ns
t
RHQX
RD Data Hold Time
(Note
1
)
0
0
0
ns
t
RLRH
RD Pulse Width
(Note
1
)
27
32
38
ns
t
RHQZ
RD to Data High-Z
(Note
1
)
20
25
30
ns
t
EHEL
E Pulse Width
27
32
38
ns
t
THEH
R/W Setup Time to Enable
6
10
18
ns
t
ELTL
R/W Hold Time After Enable
0
0
0
ns
t
AVPV
Address Input Valid to
Address Output Delay
(Note
4
)
20
25
30
ns
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