- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376291 > PSD913515MIT (意法半導(dǎo)體) BBG ECL/TTL CLOCK DRVR; Package: 28 LEAD PLCC; No of Pins: 28; Container: Tape and Reel; Qty per Container: 500 PDF資料下載
參數(shù)資料
| 型號(hào)： | PSD913515MIT |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | BBG ECL/TTL CLOCK DRVR; Package: 28 LEAD PLCC; No of Pins: 28; Container: Tape and Reel; Qty per Container: 500 |
| 中文描述： | Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器 |
| 文件頁(yè)數(shù)： | 50/110頁(yè) |
| 文件大小： | 1737K |
| 代理商： | PSD913515MIT |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)當(dāng)前第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
50/110
68HC11
Figure
25
shows a bus interface to a 68HC11
where the PSD is configured in 8-bit multiplexed
mode with E and R/W settings. The DPLD can be
used to generate the READ and WR signals for
external devices.
Figure 25. Interfacing the PSD with a 68HC11
9
10
11
12
13
14
15
16
ADIO0
ADIO1
ADIO2
ADIO3
AD104
AD105
ADIO6
ADIO7
ADIO8
ADIO9
ADIO10
ADIO11
AD1012
AD1013
ADIO14
ADIO15
CNTL0(R_W)
CNTL1(E)
CNTL2
PD0–AS
PD1
PD2
RESET
20
21
22
23
24
25
3
5
4
6
42
41
40
39
38
37
36
35
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
A8
A9
A10
A11
A12
A14
A15
A13
E
AS
R/W
XT
EX
RESET
IRQ
XIRQ
PA0
PA1
PA2
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
VRH
VRL
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PD0
PD1
PD2
PD3
PD4
PD5
MODA
E
AS
R/W
31
30
29
28
27
30
31
32
33
34
35
36
37
39
40
41
42
43
44
45
46
48
8
9
10
49
50
47
8
7
17
19
18
34
33
32
43
44
45
46
47
48
49
50
52
51
29
28
27
25
24
23
22
21
20
19
18
17
14
13
12
11
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
7
6
5
4
3
2
52
51
MODB
2
68HC11
PSD
RESET
RESET
AD7-AD0
AD7-AD0
AI02884C
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD913515MT | BBG ECL/TTL CLOCK DRVR; Package: 28 LEAD PLCC; No of Pins: 28; Container: Rail; Qty per Container: 37 |
| PSD913520JIT | ECL/TTL Clock Driver; Package: 28 LEAD PLCC; No of Pins: 28; Container: Tape and Reel; Qty per Container: 500 |
| PSD913520JT | BBG ECL/TTL CLOCK DRVR; Package: 28 LEAD PLCC; No of Pins: 28; Container: Tape and Reel; Qty per Container: 500 |
| PSD913520MIT | 1:8 Clock Driver; Package: 28 LEAD PLCC; No of Pins: 28; Container: Rail; Qty per Container: 37 |
| PSD913520MT | BBG ECL/TTL CLOCK DRVR; Package: 28 LEAD PLCC; No of Pins: 28; Container: Rail; Qty per Container: 37 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD913515MT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913520JIT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913520JT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913520MIT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913520MT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。