- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376291 > PSD913590MIT (意法半導體) BBG ECL CLOCK DIST CHIP; Package: 28 LEAD PLCC; No of Pins: 28; Container: Rail; Qty per Container: 37 PDF資料下載
參數(shù)資料
| 型號： | PSD913590MIT |
| 廠商： | 意法半導體 |
| 英文描述： | BBG ECL CLOCK DIST CHIP; Package: 28 LEAD PLCC; No of Pins: 28; Container: Rail; Qty per Container: 37 |
| 中文描述： | Flash在系統(tǒng)可編程ISP的外設的8位微控制器 |
| 文件頁數(shù)： | 13/110頁 |
| 文件大小： | 1737K |
| 代理商： | PSD913590MIT |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁當前第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁
13/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Note: 1. The pin numbers in this table are for the PLCC package only. See the package information from
Table 74., page 102
onwards, for
pin numbers on other package types.
2. These functions can be multiplexed with other functions.
PC7
11
I/O
PC7 pin of Port C. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellBC7) output.
Input to the PLDs.
DBE – active Low Data Byte Enable input from 68HC912 type MCUs.
This pin can be configured as a CMOS or Open Drain output.
PD0
10
I/O
PD0 pin of Port D. This port pin can be configured to have the following functions:
ALE/AS input latches address output from the MCU.
MCU I/O – write or read from a standard output or input port.
Input to the PLDs.
CPLD output (External Chip Select).
PD1
9
I/O
PD1 pin of Port D. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
Input to the PLDs.
CPLD output (External Chip Select).
CLKIN – clock input to the CPLD macrocells, the APD Unit’s Power-down counter, and
the CPLD AND Array.
PD2
8
I/O
PD2 pin of Port D. This port pin can be configured to have the following functions:
MCU I/O - write to or read from a standard output or input port.
Input to the PLDs.
CPLD output (External Chip Select).
PSD Chip Select Input (CSI). When Low, the MCU can access the PSD memory and I/O.
When High, the PSD memory blocks are disabled to conserve power.
V
CC
15, 38
Supply Voltage
GND
1, 16,
26
Ground pins
Pin Name
Pin
Type
Description
相關PDF資料 |
PDF描述 |
|---|---|
| PSD913590MT | PECL/TTL-TTL 1:8 Distribution Chip; Package: 28 LEAD PLCC; No of Pins: 28; Container: Tape and Reel; Qty per Container: 500 |
| PSD833F2-12J | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD853F2-12J | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD833F2-12JI | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD853F2-12JI | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PSD913590MT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD9135V12JIT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD9135V12JT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD9135V12MIT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD9135V12MT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
發(fā)布緊急采購，3分鐘左右您將得到回復。