- 您現在的位置：買賣IC網 > PDF目錄376275 > PSD9135V15MT (意法半導體) Quad Bus TRS/Rectifier ECL Differential; Package: 28 LEAD PLCC; No of Pins: 28; Container: Tape and Reel; Qty per Container: 500 PDF資料下載
參數資料
| 型號： | PSD9135V15MT |
| 廠商： | 意法半導體 |
| 英文描述： | Quad Bus TRS/Rectifier ECL Differential; Package: 28 LEAD PLCC; No of Pins: 28; Container: Tape and Reel; Qty per Container: 500 |
| 中文描述： | Flash在系統可編程ISP的外設的8位微控制器 |
| 文件頁數： | 53/110頁 |
| 文件大小： | 1737K |
| 代理商： | PSD9135V15MT |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁當前第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁
53/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
MCU I/O Mode
In the MCU I/O mode, the MCU uses the I/O Ports
block to expand its own I/O ports. By setting up the
CSIOP space, the ports on the PSD are mapped
into the MCU address space. The addresses of
the ports are listed in
Table 7., page 18
.
A port pin can be put into MCU I/O mode by writing
a 0 to the corresponding bit in the Control Regis-
ter. The MCU I/O direction may be changed by
writing to the corresponding bit in the Direction
Register, or by the output enable product term.
See
the
section
entitled
Mode, page 55
. When the pin is configured as an
output, the content of the Data Out Register drives
the pin. When configured as an input, the MCU
can read the port input through the Data In buffer.
See
Figure 26., page 52
.
Ports C and D do not have Control Registers, and
are in MCU I/O mode by default. They can be used
for PLD I/O if equations are written for them in PS-
Dabel.
PLD I/O Mode
The PLD I/O Mode uses a port as an input to the
CPLD’s Input Macrocells (IMC), and/or as an out-
put from the CPLD’s Output Macrocells (OMC).
The output can be tri-stated with a control signal.
This output enable control signal can be defined
by a product term from the PLD, or by resetting the
Peripheral
I/O
corresponding bit in the Direction Register to ’0.’
The corresponding bit in the Direction Register
must not be set to '1' if the pin is defined for a PLD
input signal in PSDabel. The PLD I/O mode is
specified in PSDabel by declaring the port pins,
and then writing an equation assigning the PLD I/
O to a port.
Address Out Mode
For MCUs with a multiplexed address/data bus,
Address Out Mode can be used to drive latched
addresses on to the port pins. These port pins can,
in turn, drive external devices. Either the output
enable or the corresponding bits of both the Direc-
tion Register and Control Register must be set to
a 1 for pins to use Address Out Mode. This must
be done by the MCU at run-time. See Table
21
for
the address output pin assignments on Ports A
and B for various MCUs.
For non-multiplexed 8-bit bus mode, address sig-
nals (A7-A0) are available to Port B in Address Out
Mode.
Note:
Do not drive address signals with Address
Out Mode to an external memory device if it is in-
tended for the MCU to Boot from the external de-
vice. The MCU must first Boot from PSD memory
so the Direction and Control register bits can be
set.
Table 19. Port Operating Modes
Note: 1. Can be multiplexed with other I/O functions.
Port Mode
Port A
Port B
Port C
Port D
MCU I/O
Yes
Yes
Yes
Yes
PLD I/O
McellAB Outputs
McellBC Outputs
Additional Ext. CS Outputs
PLD Inputs
Yes
No
No
Yes
Yes
Yes
No
Yes
No
Yes
No
Yes
No
No
Yes
Yes
Address Out
Yes (A7 – 0)
Yes (A7 – 0)
or (A15 – 8)
No
No
Address In
Yes
Yes
Yes
Yes
Data Port
Yes (D7 – 0)
No
No
No
Peripheral I/O
Yes
No
No
No
JTAG ISP
No
No
Yes
1
No
相關PDF資料 |
PDF描述 |
|---|---|
| PSD9135V20JIT | 2.5V / 3.3V ECL 1:2 Differential Fanout Buffer; Package: SOIC-8 Narrow Body; No of Pins: 8; Container: Rail; Qty per Container: 98 |
| PSD9135V20JT | 2.5V / 3.3V ECL 1:2 Differential Fanout Buffer; Package: SOIC-8 Narrow Body; No of Pins: 8; Container: Rail; Qty per Container: 98 |
| PSD9135V20MIT | 2.5V / 3.3V ECL 1:2 Differential Fanout Buffer; Package: SOIC-8 Narrow Body; No of Pins: 8; Container: Tape and Reel; Qty per Container: 2500 |
| PSD9135V20MT | 2.5V / 3.3V ECL 1:2 Differential Fanout Buffer; Package: SOIC-8 Narrow Body; No of Pins: 8; Container: Tape and Reel; Qty per Container: 2500 |
| PSD9135V70MT | 2.5V / 3.3V ECL 1:2 Differential Fanout Buffer; Package: TSSOP 8 3.0x3.0x0.95 mm; No of Pins: 8; Container: Rail; Qty per Container: 100 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| PSD9135V20JIT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD9135V20JT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD9135V20MIT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD9135V20MT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD9135V70JIT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
發布緊急采購，3分鐘左右您將得到回復。