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參數資料
| 型號： | PSD935F3V-15UI |
| 廠商： | 意法半導體 |
| 英文描述： | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| 中文描述： | 在8片位微控制器可配置存儲系統 |
| 文件頁數： | 7/91頁 |
| 文件大小： | 488K |
| 代理商： | PSD935F3V-15UI |
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PSD9XX
Architectural
Overview
(cont.)
4.5 ISP via JTAG Port
In-System Programming can be performed through the JTAG pins on Port E. This serial
interface allows complete programming of the entire PSD935G2 device. A blank device
can be completely programmed. The JTAG signals (TMS, TCK, TSTAT, TERR, TDI, TDO)
can be multiplexed with other functions on Port E. Table 3 indicates the JTAG signals pin
assignments.
4.6 In-System Programming (ISP)
Using the JTAG signals on Port E, the entire PSD935G2 (memory, logic, configuration)
device can be programmed or erased without the use of the microcontroller.
Port E Pins
PE0
PE1
PE2
PE3
PE4
PE5
JTAG Signal
TMS
TCK
TDI
TDO
TSTAT
TERR
Table 3. JTAG Signals on Port E
PSD9XX Family
PSD935G2
6
4.7 In-Application re-Programming (IAP)
The main Flash memory can also be programmed in-system by the microcontroller
executing the programming algorithms out of the secondary Flash memory, or SRAM.
Since this is a sizable separate block, the application can also continue to operate. The
secondary Flash boot memory can be programmed the same way by executing out of the
main Flash memory. Table 4 indicates which programming methods can program different
functional blocks of the PSD9XX.
Device
Programmer
Yes
Yes
Yes
Yes
Functional Block
Main Flash memory
Flash Boot memory
PLD Array (DPLD and GPLD)
PSD Configuration
JTAG-ISP
Yes
Yes
Yes
Yes
IAP
Yes
Yes
No
No
Table 4. Methods of Programming Different Functional Blocks of the PSD935G2
4.8 Page Register
The eight-bit Page Register expands the address range of the microcontroller by up to
256 times.The paged address can be used as part of the address space to access
external memory and peripherals or internal memory and I/O. The Page Register can also
be used to change the address mapping of blocks of Flash memory into different memory
spaces for IAP.
4.9 Power Management Unit
The Power Management Unit (PMU) in the PSD935G2 gives the user control of the
power consumption on selected functional blocks based on system requirements. The
PMU includes an Automatic Power Down unit (APD) that will turn off device functions due
to microcontroller inactivity. The APD unit has a Power Down Mode that helps reduce
power consumption.
The PSD935G2 also has some bits that are configured at run-time by the MCU to reduce
power consumption of the GPLD. The turbo bit in the PMMR0 register can be turned off
and the GPLD will latch its outputs and go to standby until the next transition on its inputs.
Additionally, bits in the PMMR2 register can be set by the MCU to block signals from
entering the GPLD to reduce power consumption. See section 9.5.
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| PSD954F2-90J | 功能描述:SPLD - 簡單可編程邏輯器件 U 511-PSD854F2-90J RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD954F2-90M | 功能描述:SPLD - 簡單可編程邏輯器件 U 511-PSD854F2-90M RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
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