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參數(shù)資料
型號(hào)： PSD953290MT
廠商： 意法半導(dǎo)體
英文描述： High Speed CMOS Logic Quad Two-Input NOR Gates 14-SOIC -55 to 125
中文描述： Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
文件頁(yè)數(shù)： 56/110頁(yè)
文件大小： 1737K
代理商： PSD953290MT
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
56/110
JTAG In-System Programming (ISP)
Port C is JTAG compliant, and can be used for In-
System Programming (ISP). You can multiplex
JTAG operations with other functions on Port C
because In-System Programming (ISP) is not per-
formed in normal Operating mode. For more infor-
mation on the JTAG Port, see the section entitled
PROGRAMMING IN-CIRCUIT USING THE JTAG
SERIAL INTERFACE, page 69
.
Port Configuration Registers (PCR)
Each Port has a set of Port Configuration Regis-
ters (PCR) used for configuration. The contents of
the registers can be accessed by the MCU through
normal READ/WRITE bus cycles at the addresses
given in
Table 7., page 18
. The addresses in Ta-
ble
7
are the offsets in hexadecimal from the base
of the CSIOP register.
The pins of a port are individually configurable and
each bit in the register controls its respective pin.
For example, Bit 0 in a register refers to Bit 0 of its
port. The three Port Configuration Registers
(PCR), shown in Table
22
, are used for setting the
Port configurations. The default Power-up state for
each register in Table
22
is 00h.
Control Register
Any bit reset to '0' in the Control Register sets the
corresponding port pin to MCU I/O Mode, and a '1'
sets it to Address Out Mode. The default mode is
MCU I/O. Only Ports A and B have an associated
Control Register.
Direction Register
The Direction Register, in conjunction with the out-
put enable (except for Port D), controls the direc-
tion of data flow in the I/O Ports. Any bit set to '1'
in the Direction Register causes the correspond-
ing pin to be an output, and any bit set to '0' causes
it to be an input. The default mode for all port pins
is input.
Figure 28., page 58
and
Figure 29., page 59
show
the Port Architecture diagrams for Ports A/B and
C, respectively. The direction of data flow for Ports
A, B, and C are controlled not only by the direction
register, but also by the output enable product
term from the PLD AND Array. If the output enable
product term is not active, the Direction Register
has sole control of a given pin’s direction.
An example of a configuration for a Port with the
three least significant bits set to output and the re-
mainder set to input is shown in Table
25
. Since
Port D only contains three pins (shown in
Figure
31., page 61
), the Direction Register for Port D
has only the three least significant bits active.
Drive Select Register
The Drive Select Register configures the pin driver
as Open Drain or CMOS for some port pins, and
controls the slew rate for the other port pins. An
external pull-up resistor should be used for pins
configured as Open Drain.
A pin can be configured as Open Drain if its corre-
sponding bit in the Drive Select Register is set to a
’1.’ The default pin drive is CMOS.
Note that the slew rate is a measurement of the
rise and fall times of an output. A higher slew rate
means a faster output response and may create
more electrical noise. A pin operates in a high slew
rate when the corresponding bit in the Drive Reg-
ister is set to ’1.’ The default rate is slow slew.
Table 26., page 57
shows the Drive Register for
Ports A, B, C, and D. It summarizes which pins can
be configured as Open Drain outputs and which
pins the slew rate can be set for.
Table 22. Port Configuration Registers (PCR)
Note: 1. See
Table 26., page 57
for Drive Register bit definition.
Table 23. Port Pin Direction Control, Output
Enable P.T. Not Defined
Table 24. Port Pin Direction Control, Output
Enable P.T. Defined
Table 25. Port Direction Assignment Example
Register Name
Port
MCU Access
Control
A,B
WRITE/READ
Direction
A,B,C,D
WRITE/READ
Drive Select
1
A,B,C,D
WRITE/READ
Direction Register Bit
Port Pin Mode
0
Input
1
Output
Direction
Register Bit
Output Enable
P.T.
Port Pin Mode
0
0
Input
0
1
Output
1
0
Output
1
1
Output
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0
0
0
0
0
1
1
1
相關(guān)PDF資料
PDF描述
PSD9532V12JT High Speed CMOS Logic Quad Two-Input NOR Gates 14-SOIC -55 to 125
PSD9532V12MIT High Speed CMOS Logic Quad Two-Input NOR Gates 14-SOIC -55 to 125
PSD9532V12MT Flash In-System Programmable ISP Peripherals For 8-bit MCUs
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