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參數資料
| 型號： | PSN1810A |
| 廠商： | Z-Communications, Inc. |
| 英文描述： | LOW COST - HIGH PERFORMANCE PHASE LOCKED LOOP |
| 中文描述： | 低成本-高性能鎖相環 |
| 文件頁數： | 1/2頁 |
| 文件大小： | 81K |
| 代理商： | PSN1810A |
100 Hz
1 kHz
10 kHz
100 kHz
-40
-60
-100
-140
-180
-220
PSN1810A
PHASE LOCKED LOOP
Telecommunications
Satellite
Telemetry
5
34
1780
-70
4±2
50
50
1000
-101
-15
10
5
-40 to 85
Frequency Range
Harmonic Suppression (2nd, typ.)
Sideband Spurs (typ.)
Switching Speed (typ., adjacent channel)
Startup Lock Time (typ.)
Operating Temperature Range
Package Style
PLL
MHz
dBc/Hz
dBc
dBc
dBm
mSec
mSec
°C
Vdc
mA
Supply Voltage (Vcc, nom.)
Supply Current (Icc, typ.)
All specifications are typical unless otherwise noted and subject to change without notice.
PHASE NOISE (1 Hz BW, typical)
Z-Communications, Inc.
All rights reserved
Page 1
FEATURES
APPLICATIONS
PERFORMANCE SPECIFICATIONS
VALUE
1780
UNITS
POWER SUPPLY REQUIREMENTS
APPLICATION NOTES
MHz
Step Size:
PLL
50 KHz
- Style Package
A1
Rev
AN-107 : How to Solder Z-COMM VCOs / PLLs
AN-200 : Mounting and Grounding of Z-COMM PLLs
AN-201 : PLL Fundamentals AN-202 : PLL Functional Description
NOTES:
Reference Oscillator Signal: 5 MHz<
f
osc
<40 MHz
Frequency Synthesizer: National Semiconductor - LMX2326
9939 Via Pasar San Diego, CA 92126
TEL (858) 621-2700 FAX (858) 621-2722
Power Output
Load Impedance
Step Size
KHz
μΑ
1840
-
Frequency Range:
-
1840
Charge Pump Output Current
Phase Noise @ 10 kHz offset (1 Hz BW, typ.)
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