
For technical support and more information, see inside back cover or visit www.ti.com
Ordering Information
PT 5041
= +12 Volts
PT 5042
= +15 Volts
PT 5044
= +8 Volts
PT 5045
= +9 Volts
PT 5046
= +10 Volts
PT 5047
= +18 Volts
PT 5048
= +12.6 Volts
PT 5049
= +20 Volts
Pin-Out Information
Pin
Function
1
V
in
2
GND
3
V
out
Standard Application
C
1
= Optional ceramic (1-5μF)
C
2
= Optional ceramic (1-5μF)
C
3
= Required Electrolytic (100μF)
NOTE: Boost Topology ISRs are not Short-Circuit Protected.
Features
Wide Input Voltage Range
85% Efficiency
Internal Over-Temperature
Protection
Laser-trimmed Output Voltage
Soft Start
5-Pin Mount Option
(Suffixes L & M)
1-A Positive Step-up
Integrated Switching Regulator
PT5040 Series
SLTS026B
(Revised 12/19/2001)
PT Series Suffix
(PT1234
x
)
Case/Pin
Configuration
Vertical
Horizontal
SMD
Horizontal, 2-pin Tab
SMD, 2-Pin Tab
* Previously known as package styles 100/110.
(Reference the applicable package code drawing
for the dimensions and PC board layout)
Order
Suffix
N
A
C
M
L
Package
C ode *
(EAD)
(EAA)
(EAC)
(EAM)
(EAL)
Description
The PT5040 is a series of 3-pin
boost-voltage Integrated Switching
Regulators (ISRs). These ISRs are
designed for use with +5V bus systems
that require an additional regulated
+8V to +20V with up to 1A of output
current. These ISRs are packaged in
the 3-pin, single in-line pin (SIP)
package configuration.
Specifications
(Unless otherwise stated, T
a
=25°C, V
in
=5V, I
o
=I
o
max, C
3
=100μF)
PT5040 SERIES
Typ
—
—
—
—
—
—
—
—
Characteristics
Output Current
Symbol
I
o
Conditions
Over V
in
range
Min
Max
0.5
0.6
1.0
0.75
1.5
1.2
(V
o
–
1)
14
Units
PT5049
PT5047
PT5041/48
PT5042
PT5044
PT5045/46
0.1
(1)
0.1
(1)
0.1
(1)
0.1
(1)
0.1
(1)
0.1
(1)
4.75
4.75
A
Input Voltage Range
V
in
Over Io range
V
PT5047/5049
Output Voltage Tolerance
V
o
Over V
Range
T
a
= -20°C to SOA derating limit
(3)
Over V
in
range
I
o
min
≤
I
o
≤
I
o
max
I
o
=0.5A
20MHz bandwidth
25% load change
V
o
over/undershoot
—
—
—
—
—
—
—
—
—
±1.5
±0.5
±0.5
85
±2
500
3.0
150
(2)
5.5
(3)
1
650
800
—
40
±3.0
±1.0
±1.0
—
±5
—
5.0
—
—
%V
o
%V
o
%V
o
%
%V
o
μSec
%V
o
%I
o
max
A
mSec
Line Regulation
Load Regulation
Efficiency
V
o
Ripple (pk-pk)
Transient Response
Reg
line
Reg
load
η
V
r
t
tr
V
os
I
lim
I
ir
t
ir
s
Current Limit
Inrush Current
On start up
Switching Frequency
Over V
in
and I
o
ranges
V
o
<15V
V
o
>15V
500
650
-20
—
800
950
+85
(4)
—
kHz
Operating Temperature Range
Thermal Resistance
T
a
θ
ja
—
Free Air Convection
(40-60LFM)
°C
°C/W
Storage Temperature
Mechanical Shock
T
s
-40
—
+125
°C
Per Mil-STD-883D, Method 2002.3
1 msec, Half Sine, mounted to a fixture
Suffixes N, A, & C
Suffixes L & M
Suffixes N, A, & C
Suffixes L & M
—
500
—
—
—
—
—
5
20
(5)
4.5
6.5
G’s
—
—
—
—
Mechanical Vibration
Per Mil-STD-883D, 20-2000 Hz
Weight
G’s
grams
Notes:
(1) The ISR will operate at no load with reduced specifications.
(2) Boost topology ISRs are not short circuit protected.
(3) The inrush current stated is above the normal input current for the associated output load.
(4) See Safe Operating Area curves or consult the factory for the appropriate derating
(5) The tab pins on the 5-pin mount package types (suffixes L & M) must be soldered. For more information see the applicable package outline drawing.
PT5040
3
2
1
C
100μF
+
C
2
+V
out
COM
COM
+V
in
C
1