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參數(shù)資料
| 型號： | Q532805SO |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER |
| 中文描述： | 保證低至3.3V的CMOS斜時鐘驅(qū)動器/緩沖器 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大小： | 97K |
| 代理商： | Q532805SO |
1
QS532805/A/B
GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
JULY 2000
1999 Integrated Device Technology, Inc.
DSC-5785/-
c
QS532805/A/B
INDUSTRIAL TEMPERATURE RANGE
GUARANTEED LOW SKEW
3.3V CMOS CLOCK
DRIVER/BUFFER
FUNCTIONAL BLOCK DIAGRAM
OEA
INA
INB
OA5
OA1
5
5
MON
OB5
OB1
OEB
DESCRIPTION
The QS532805 clock buffer/driver circuits can be used for clock buffering
schemes where low skew is a key parameter. This device offers two banks
of 5 non-inverting outputs. The QS532805 incorporates 25
series
termnation resistors. This clock buffer product is designed for use in high
performance workstations, embedded and personal computing systems
using 3V to 3.6V supply voltages. Several can be used in parallel or
scattered throughout a systemfor guaranteed low skew, system-wide clock
distribution networks. The QS532805 can accept 5V input and control
signals.
The QS532805 is characterized for operation at -40°C to +85°C.
FEATURES:
JEDEC compatible LVTTL level inputs and outputs
10 output, low skew clock signal buffer
Monitor output
Clock inputs are 5V tolerant
Pinout and function compatible with QS5805T
25
on-chip resistors for low noise
Input hysteresis for better noise margin
Guaranteed low skew:
0.7ns output skew
0.7ns pulse skew
1ns part-to-part skew
Std., A, and B speed grades (B speed in QSOP package only)
Available in QSOP and SOIC packages
NOTE:
QS532805 has a 25
series termination resistor on each clock output, including monitor.
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