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參數資料
| 型號： | Q62705-K174 |
| 廠商： | SIEMENS AG |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | Advanced PFC/PWM Combination Controllers 20-PDIP -40 to 105 |
| 中文描述： | 相對硅壓阻壓力傳感器 |
| 文件頁數： | 4/12頁 |
| 文件大小： | 71K |
| 代理商： | Q62705-K174 |
Data Book
4
2003-05
KP110
Functional Description
Digital Programming Interface
The KP110 digital interface is a 3 wire interface consisting of Data_In, Data_Out and
Clock. A write cycle needs 13 Clock cycles. With the first 12 rising edges of the Clock the
signal on Data_In is clocked into a shift register. The first 3 bits are interpreted as a
register address, the last 9 as data bits. The address and the data word are starting with
the LSB, respectively. During the falling edges of the first 11 Clock cycles the Data_In
must be low. The falling edge of the 12th Clock cycle enables the write frame, at this time
Data_In must be high. A 13th Clock cycle is needed for internal purposes, the signal at
Data_In is ignored.
Simultaneously to the write cycle, a read cycle at Data_Out is performed. The signal at
Data_Out is structured the same way as at Data_In, i.e. 3 address bits and 9 data bits.
The selected register for reading depends on the content of the TESTREG register.
The first valid bit at Data_Out appears with the 13th rising edge of the Clock of the
previous write frame.
The following figure shows the timing diagram:
Figure 3
Timing Diagram
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