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參數資料
| 型號： | Q67000-A9210-C801 |
| 廠商： | SIEMENS AG |
| 英文描述： | 5-V Low-Drop Fixed Voltage Regulator |
| 中文描述： | 5 - V低拖放固定穩壓器 |
| 文件頁數： | 3/20頁 |
| 文件大小： | 128K |
| 代理商： | Q67000-A9210-C801 |
TLE 4271
Semiconductor Group
3
1998-11-01
Application Description
The IC regulates an input voltage in the range of 5.5 V <
V
I
< 36 V to
V
Qnom
= 5.0 V. Up
to 26 V it produces a regulated output current of more than 550 mA. Above 26 V the
save-operating-area protection allows operation up to 36 V with a regulated output
current of more than 300 mA. Overvoltage protection limits operation at 42 V. The
overvoltage protection hysteresis restores operation if the input voltage has dropped
below 36 V. The IC can be switched off via the inhibit input, which causes the quiescent
current to drop below 50
μ
A. A reset signal is generated for an output voltage of
V
Q
< 4.5 V. The watchdog circuit monitors a connected controller. If there is no positive-
going edge at the watchdog input within a fixed time, the reset output is set to low. The
delay for power-on reset and the maximum permitted watchdog-pulse period can be set
externally with a capacitor.
Design Notes for External Components
An input capacitor
C
I
is necessary for compensation of line influences. The resonant
circuit consisting of lead inductance and input capacitance can be damped by a resistor
of approx. 1
in series with
C
I
. An output capacitor
C
Q
is necessary for the stability of
the regulating circuit. Stability is guaranteed at values of
C
Q
≥
22
μ
F and an ESR of
< 3
.
Circuit Description
The control amplifier compares a reference voltage, which is kept highly accurate by
resistance adjustment, to a voltage that is proportional to the output voltage and drives
the base of a series transistor via a buffer. Saturation control as a function of the load
current prevents any over-saturation of the power element.
If the output voltage decreases below 4.5 V, an external capacitor
C
D
on pin 4 (D) will be
discharged by the reset generator. If the voltage on this capacitor
V
D
drops below
V
DRL
,
a reset signal is generated on pin 2 (RO), i.e. reset output is set low. If the output voltage
rises above 4.5 V,
C
D
will be charged with constant current. After the power-on-reset time
V
D
reaches
V
DU
and the reset output will be set high again. The value of the power-on-
reset time can be set within a wide range depending on the capacity of
C
D
. The value of
the pull-up resistor at reset output is typically 30 k
.
After
V
D
has reached the voltage
V
DU
and reset was set to high, the watchdog circuit is
enabled and discharges
C
D
with a constant current. If there is no positive-going edge
observed at watchdog input,
C
D
will be discharged down to
V
DWL
. Then reset will be set
low and the watchdog circuit will be disabled.
C
D
will be charged with the current as at
power-on reset until
V
D
reaches
V
DU
and reset will be set high again.
If a watchdog pulse will be observed before
C
D
is discharged down to
V
DWL
, the watchdog
circuit will be enabled and
C
D
will be charged too, but reset will not be set low. After
V
D
has reached
V
DU
, the periodical behavior starts again.
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