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參數(shù)資料
| 型號(hào)： | Q67060-S6302-A2 |
| 廠商： | SIEMENS AG |
| 英文描述： | High Speed CMOS Logic Dual 4-Stage Static Shift Registers 16-PDIP -55 to 125 |
| 中文描述： | 智能雙通道阻抗高側(cè)電源開關(guān) |
| 文件頁(yè)數(shù)： | 8/14頁(yè) |
| 文件大?。?/td> | 191K |
| 代理商： | Q67060-S6302-A2 |
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BTS 611 L1
Semiconductor Group
8
Status output
ST
GND
ESD-
ZD
+5V
R
ST(ON)
ESD-Zener diode: 6.1 V typ., max 5 mA;
R
ST(ON)
< 380
at 1.6 mA, ESD zener diodes are not
to be used as voltage clamp at DC conditions.
Operation in this mode may result in a drift of the zener
voltage (increase of up to 1 V).
Inductive and overvoltage output clamp
+ Vbb
OUT
GND
PROFET
VZ
V
ON
V
ON
clamped to 47 V typ.
Overvolt. and reverse batt. protection
+ Vbb
IN2
ST
ST
R
GND
GND
R
Signal GND
Logic
VZ2
IN1
RI
VZ1
V
Z1
= 6.1 V typ., V
Z2
= 47 V typ., R
I
= 3.5 k
typ
,
R
GND
= 150
Open-load detection
ON-state diagnostic condition: V
ON
< R
ON
* I
L(OL)
; IN
high
Open load
detection
Logic
unit
+ Vbb
OUT
ON
V
ON
OFF-state diagnostic condition: V
OUT
> 3 V typ.; IN low
Open load
detection
Logic
unit
VOUT
Signal GND
REXT
RO
OFF
GND disconnect
PROFET
V
IN2
ST
OUT2
GND
bb
Vbb
Ibb
1
2
4
3
5
IN1
OUT1
6
7
VIN1VIN2VST
VGND
Any kind of load. In case of Input=high is V
OUT
≈
V
IN
- V
IN(T+)
.
Due to V
GND
>0, no V
ST
= low signal available.
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