- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄361232 > Q67100-Q1072 (SIEMENS AG) 1M x 16-Bit Dynamic RAM 1k Refresh PDF資料下載
參數(shù)資料
| 型號(hào)： | Q67100-Q1072 |
| 廠商： | SIEMENS AG |
| 英文描述： | 1M x 16-Bit Dynamic RAM 1k Refresh |
| 中文描述： | 100萬(wàn)× 16位動(dòng)態(tài)隨機(jī)存儲(chǔ)器經(jīng)銷商刷新 |
| 文件頁(yè)數(shù)： | 1/53頁(yè) |
| 文件大?。?/td> | 418K |
| 代理商： | Q67100-Q1072 |
當(dāng)前第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)
HYB 39S64400/800/160BT(L)
64-MBit Synchronous DRAM
Data Book
1
12.99
The HYB 39S64400/800/160BT are four bank Synchronous DRAM’s organized as
4 banks
×
4MBit
×
4, 4 banks
×
2 MBit
×
8 and 4 banks
×
1 Mbit
×
16 respectively. These synchron-
ous devices achieve high speed data transfer rates by employing a chip architecture that prefects
multiple bits and then synchronizes the output data to a system clock. The chip is fabricated using
the Infineon advanced 0.2
μ
m 64 MBit DRAM process technology.
The device is designed to comply with all JEDEC standards set for Synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur
at higher rates than is possible with standard DRAMs. A sequential and gapless data rate is
possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operates with a
single 3.3 V
±
0.3 V power supply and are available in TSOPII packages.
High Performance:
Fully Synchronous to Positive Clock Edge
0 to 70
°
C operating temperature
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 3
Programmable Wrap Sequence: Sequential
or Interleave
Programmable Burst Length: 1, 2, 4, 8
Full page (optional) for sequential wrap
around
Multiple Burst Read with Single Write
Operation
Automatic and Controlled Precharge
Command
Data Mask for Read/Write Control (x4, x8)
Data Mask for Byte Control (x16)
Auto Refresh (CBR) and Self Refresh
Suspend Mode and Power Down Mode
4096 Refresh Cycles / 64 ms
Random Column Address every CLK
(1-N Rule)
Single 3.3 V
±
0.3 V Power Supply
LVTTL Interface
Plastic Packages:
P-TSOPII-54 400mil width (x4, x8, x16)
-7.5 version for PC133 3-3-3 application
-8 version for PC100 2-2-2 applications
-7.5
-8
Units
f
CKMAX
133
125
MHz
t
CK3
7.5
8
ns
t
AC3
5.4
6
ns
t
CK2
10
10
ns
t
AC2
6
6
ns
64-MBit Synchronous DRAM
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Q67100-Q1073 | 1M x 16-Bit Dynamic RAM 1k Refresh |
| Q67100-Q1074 | 1M x 16-Bit Dynamic RAM |
| Q67100-Q1086 | 4M x 4-Bit Dynamic RAM 2k & 4k Refresh |
| Q67100-Q1087 | 4M x 4-Bit Dynamic RAM 2k & 4k Refresh |
| Q67100-Q1088 | 4M x 4-Bit Dynamic RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| Q67100-Q1073 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM |
| Q67100-Q1074 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM |
| Q67100-Q1086 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:4M x 4-Bit Dynamic RAM |
| Q67100-Q1087 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:4M x 4-Bit Dynamic RAM |
| Q67100-Q1088 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:4M x 4-Bit Dynamic RAM |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。