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參數(shù)資料
| 型號(hào)： | Q67103-H6594 |
| 廠商： | SIEMENS AG |
| 英文描述： | Memory Time Switch Extended Large MTSXL |
| 中文描述： | 內(nèi)存定時(shí)開關(guān)擴(kuò)展大型MTSXL |
| 文件頁數(shù)： | 24/51頁 |
| 文件大小： | 1052K |
| 代理商： | Q67103-H6594 |
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PEB 2447
Operational Description
Semiconductor Group
24
03.97
Typical Write Operation:
WR MWDL
WR MWDH
WR MAAL
WR MACH
Typical Read Operation:
WR MAAL
WR MACH
RD STAR; STAR:MAC = 0
RD MRDL
RD MRDH
RD STAR; STAR:MAC = 0
3.4
If the device is in synchronized state (STAR:PSS = 1) and for example the command
“frame evaluation at FS5” (CMDR = 58
H
) is programmed, the second following rising
edge of FS5 is evaluated and creates the following result in register FERH:FERL (see
also
table 15
):
Frame Evaluation
Figure 8
Frame Evaluation
Note: The frame evaluation procedure gives (roughly) the number to be programmed in
ICSR (after inversion of FER0): FEV 11..1 give the number of complete CLK
periods; FEV 0 gives the sampling edge (falling / rising). Due to the internal delay
in the MTSXL the sampling region and therefor the result in FEV 11..1 is shifted
against CLK for a time
“X” which is uncertain between 0 < X < 13 ns. If the rising
edge of FS occurs in that uncertain region the value of FER 11..1 might vary + 1
(FER 0 inverted before!).
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