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參數資料
| 型號： | Q67120-C1002 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | High Speed CMOS Logic 8-Bit Addressable Latch 16-SOIC -55 to 125 |
| 中文描述： | 8位CMOS微控制器 |
| 文件頁數： | 11/24頁 |
| 文件大小： | 980K |
| 代理商： | Q67120-C1002 |
C167CS-xC Bare Die
Step BA
Data Sheet
7
V1.0, 2001-08
P3.4
33
I/O
5900
0 Port 3 input/output (open drain, sp. threshold),
Timer T3 ext.up/down T3EUD.
0 Port 3 input/output (open drain, sp. threshold),
Timer T4 Input T4IN.
0 Digital Ground.
0 Digital Supply Voltage.
498 Port 3 input/output (open drain, sp. threshold),
Timer T3 Input T3IN.
695 Port 3 input/output (open drain, sp. threshold),
Timer T2 Input T2IN.
892 Port 3 input/output (open drain, sp. threshold),
SSC Master-Rec./Slave-Transmit I/O MRST.
1090 Port 3 input/output (open drain, sp. threshold),
SSC Master-Transmit/Slave-Rec. O/I MTSR.
1287 Port 3 input/output (open drain, sp. threshold),
ASC0 Clock/Data Output (Asyn./Syn.) TxD0.
1484 Port 3 input/output (open drain, sp. threshold),
ASC0 Data Input (Asyn.) or I/O (Syn.) RxD0.
1681 Port 3 input/output (open drain, sp. threshold).
1878 High Byte Enable BHE,
High Byte Write Strobe WRH.
2075 Port 3 input/output (open drain, sp. threshold),
SSC Master(Slave) Clock Output(Input) SCLK.
2272 Port 3 input/output (open drain, sp. threshold).
2469 System Clock Output (=CPU Clock) CLKOUT,
Programmable Frequency Output FOUT.
2666 Digital Supply Voltage.
2837 Digital Ground.
2993 Port 4 input/output, Segment Address Line A16.
3149 Port 4 input/output, Segment Address Line A17.
3306 Port 4 input/output, Segment Address Line A18.
3462 Port 4 input/output, Segment Address Line A19.
P3.5
34
I/O
6079
SS
35
36
37
-
-
I/O
6258
6437
6936
DD
P3.6
P3.7
38
I/O
6936
P3.8
39
I/O
6936
P3.9
40
I/O
6936
P3.10
41
I/O
6936
P3.11
42
I/O
6936
P3.12
43
44
I/O
O
6936
6936
P3.13
45
I/O
6936
P3.15
46
47
I/O
O
6936
6936
DD
48
49
50
51
52
53
-
-
I/O
I/O
I/O
I/O
6936
6936
6936
6936
6936
6936
SS
P4.0
P4.1
P4.2
P4.3
Table 2
Pad Definitions and Functions
(cont
’
d)
Symbol Pad
Num
In /
Out
Position
[μm]
Function
x
y
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