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參數資料
型號: Q67120-C1011
廠商: SIEMENS AG
英文描述: High Speed CMOS Logic 8-Bit Addressable Latch 16-SOIC -55 to 125
中文描述: 8位CMOS微控制器
文件頁數: 20/24頁
文件大小: 980K
代理商: Q67120-C1011
C167CS-xC Bare Die
Step BA
Data Sheet
16
V1.0, 2001-08
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation of the C167CS-xC. All parameters specified in the following sections refer to
these operating conditions, unless otherwise noticed.
Table 6
Operating Condition Parameters
Parameter
Symbol
Limit Values
min.
Digital supply voltage
DD
4.5
Unit Notes
max.
5.5
V
Active mode,
CPUmax
= 33 MHz
PowerDown mode
Reference voltage
Per pin
2)
3)
3)
2.5
1)
1)
Output voltages and output currents will be reduced when
DD
leaves the range defined for active mode.
2)
Overload conditions occur if the standard operatings conditions are exceeded, i.e. the voltage on any pin
exceeds the specified range (i.e.
OV
currents on all pins may not exceed
50 mA
. The supply voltage must remain within the specified limits.
Proper operation is not guaranteed if overload conditions occur on functional pins such as XTAL1, RD, WR,
etc.
3)
Not 100% tested, guaranteed by design and characterization.
4)
The timing is valid for pin drivers in high current or dynamic current mode. The reduced static output current in
dynamic current mode must be respected when designing the system.
5.5
V
V
mA
mA
Digital ground voltage
Overload current
Absolute sum of overload
currents
External Load
Capacitance
Temperature of the
bottom side of the die
SS
0
OV
Σ
|
OV
|
-
-
±
5
50
DD
+0.5V or
OV
SS
-0.5V). The absolute sum of input overload
L
-
50
pF
Pin drivers in
fast edge
mode
4)
SAL-C167CS-xC...
SAK-C167CS-xC...
D
-40
-40
150
125
°
C
°
C
相關PDF資料
PDF描述
Q67120-C1017 High Speed CMOS Logic 8-Bit Addressable Latch 16-SOIC -55 to 125
Q67120-C1026 High Speed CMOS Logic 8-Bit Addressable Latch 16-SOIC -55 to 125
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相關代理商/技術參數
參數描述
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