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參數資料
| 型號： | Q67120-C2043 |
| 廠商： | SIEMENS AG |
| 英文描述： | High Speed CMOS Logic 9-Bit Odd/Even Parity Generator/Checker 14-SOIC -55 to 125 |
| 中文描述： | 8位CMOS微控制器 |
| 文件頁數： | 15/24頁 |
| 文件大小： | 980K |
| 代理商： | Q67120-C2043 |
C167CS-xC Bare Die
Step BA
Data Sheet
11
V1.0, 2001-08
P8.1
120
I/O
0
4933 Port 8 input/output,
Capt.-Input/Comp.-Output CC17IO,
CAN1 Transmit Data Output CAN1_TxD,
CAN2 Transmit Data Output CAN2_TxD.
4749 Port 8 input/output,
Capt.-Input/Comp.-Output CC18IO,
CAN1 Receive Data Input CAN1_RxD,
CAN2 Receive Data Input CAN2_RxD.
4565 Port 8 input/output,
Capt.-Input/Comp.-Output CC19IO,
CAN1 Transmit Data Output CAN1_TxD,
CAN2 Transmit Data Output CAN2_TxD.
4381 Port 8 input/output,
Capt.-Input/Comp.-Output CC20IO.
4197 Port 8 input/output,
Capt.-Input/Comp.-Output CC21IO.
4013 Port 8 input/output,
Capt.-Input/Comp.-Output CC22IO.
3829 Port 8 input/output,
Capt.-Input/Comp.-Output CC23IO.
3646 Digital Supply Voltage.
3462 Digital Ground.
3278 Port 7 input/output, (open drain, sp. threshold),
PWM Channel Output POUT0.
3094 Port 7 input/output, (open drain, sp. threshold),
PWM Channel Output POUT1.
2910 Port 7 input/output, (open drain, sp. threshold),
PWM Channel Output POUT2.
2726 Port 7 input/output, (open drain, sp. threshold),
PWM Channel Output POUT3.
2542 Port 7 input/output, (open drain, sp. threshold),
Capt.-Input/Comp.-Output CC28IO.
2358 Port 7 input/output, (open drain, sp. threshold),
Capt.-Input/Comp.-Output CC29IO.
P8.2
121
I/O
0
P8.3
122
I/O
0
P8.4
123
I/O
0
P8.5
124
I/O
0
P8.6
125
I/O
0
P8.7
126
I/O
0
DD
127
128
129
-
-
I/O
0
0
0
SS
P7.0
P7.1
130
I/O
0
P7.2
131
I/O
0
P7.3
132
I/O
0
P7.4
133
I/O
0
P7.5
134
I/O
0
Table 2
Pad Definitions and Functions
(cont
’
d)
Symbol Pad
Num
In /
Out
Position
[μm]
Function
x
y
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