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參數資料
| 型號： | Q67120-C552 |
| 廠商： | SIEMENS AG |
| 英文描述： | High Speed CMOS Logic Digital Phase-Locked-Loop 16-PDIP -55 to 125 |
| 中文描述： | 高性能32位RISC微處理器 |
| 文件頁數： | 17/24頁 |
| 文件大小： | 980K |
| 代理商： | Q67120-C552 |
C167CS-xC Bare Die
Step BA
Data Sheet
13
V1.0, 2001-08
Handling Of Unconnected Pads
Signal input stages may generate undesired switching noise and cross-current when left
open. Respect the following precautions for unconnected (not bonded) pads:
Table 3
Precautions for Unconnected Pads
Pad Type
Power Supply
Standard IO pads
Recommended Action
Always connect!
Switch to output
Related Pads
DD
,
PORT0, PORT1
1)
, P2, P3,
P4, P6, P7, P8
P5
P3.12 (43/44), P3.15 (46/47)
SS
,
AREF
,
AGND
1)
The lower part of PORT1 (P1L) may be left open and its input stages can then be disabled via P1DIDIS.
2)
Port pad is input in this case! If the port pad is used, the corresponding alternate output pad may be left open.
3)
Pin RD can be used for configuration to disable the OWD. Otherwise it is held high by an internal pullup.
Input port pads
Double-bond ports
Disable input stages via P5DIDIS
Connect port pad (43, 46), if the
alternate output (44, 47) is used.
2)
Always connect!
Always connect!
Configuration lines
Required
control lines
Optional
control lines
EA, C167CSMODE, RD
3)
XTAL1, RSTIN, NMI
Can be left open
RD
3)
, WR(L), READY, ALE,
RSTOUT
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