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參數資料
| 型號： | Q67120-C886 |
| 廠商： | SIEMENS AG |
| 英文描述： | High Speed CMOS Logic 8-Input NAND Gate 14-SOIC -55 to 125 |
| 中文描述： | 8位CMOS微控制器 |
| 文件頁數： | 22/24頁 |
| 文件大小： | 980K |
| 代理商： | Q67120-C886 |
C167CS-xC Bare Die
Step BA
Data Sheet
18
V1.0, 2001-08
Table 7
The wafers are glued to a plastic tape which is fixed within a plastic ring (see
Figure 5
).
Wafers can be shipped in one piece or sawn into individual dies.
Note: Please refer also to the document "
Bare Die Packing Information
".
Wafer Characteristics
Item
Chips per wafer
Metallization layers
Metallization material
Metallization thickness
Metallization barrier material
Metallization isolation
Metallization material on pads
Passivation
Backside metallization
1)
Inkdot diameter
Characteristic
262 (geometrically)
2
AlCu
Met1: 450 nm, Met2: 800 nm
Ti
SOG-CMP
AlSiCu (Al 98.5% - SI 1% - Cu 0.5%)
Oxide (300 nm) + nitride (500 nm)
None (silicon)
1.0 - 1.3 typical
1)
The backside of the chip can either be left unconnected or must be connected to
V
SS
.
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