
PEB 20560
Functional Block Description
Semiconductor Group
2-155
2003-08
When the XMIT FIFO and transmitter interrupts are enabled (FEWO = 1, ETBEI = 1),
XMIT interrupts will occur as follows:
a) The transmitter holding register interrupt (02) occurs when the XMIT FIFO is empty;
it is cleared as soon as the transmitter holding register is written to (1 to 16
characters may be written to the XMIT FIFO while servicing this interrupt) or the IIR
is read.
b) The transmitter FIFO empty indication will be delayed 1 character time minus the
last stop bit time whenever the following occurs: THRE = 1, and there have not been
at least two bytes at the same time in the transmit FIFO since the last THRE = 1.
The first transmitter interrupt after changing FEWO will be immediate, if it is
enabled.
Character time-out and RCVR FIFO trigger level interrupts have the same priority as the
current received data available interrupt; XMIT FIFO empty has the same priority as the
current transmitter holding register empty interrupt.
2.14.3
FIFO Polled Mode Operation
With FEWO = 1 resetting ERBFI, ETBEI, ERLSI, EDSSI or all to zero puts the UART in
the FIFO polled mode of operation. Since the RCVR and XMITTER are controlled
separately either one or both can be in the polled mode of operation.
In this mode the user’s program will check RCVR and XMITTER status via the LSR. As
stated previously:
– DR will be set as long as there is one byte in the RCVR FIFO.
– LSR1 to LSR4 will specify which error(s) has occurred. Character error status is
handled the same way as when in the interrupt mode, the IIR is not affected since
ERLSI = 0.
– THRE will indicate when the XMIT FIFO is empty.
– TEMT will indicate that both the XMIT FIFO and shift register are empty.
– EIRF will indicate whether there are any errors in the RCVR FIFO.
There is no trigger level reached or time-out condition indicated in the FIFO polled mode,
however, the RCVR and XMIT FlFOs are still fully capable of holding characters.