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參數(shù)資料
| 型號(hào)： | QL2009-XPQ208C |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 3.3V and 5.0V pASIC? 2 FPGA Combining Speed, Density, Low Cost and Flexibility |
| 中文描述： | 3.3V和5.0V帕希奇？ 2 FPGA的結(jié)合速度，密度，低成本和靈活性 |
| 文件頁(yè)數(shù)： | 1/12頁(yè) |
| 文件大小： | 272K |
| 代理商： | QL2009-XPQ208C |
QL2009
3.3V and 5.0V pASIC
2 FPGA
Combining Speed, Density, Low Cost and Flexibility
3-35
Ultimate Verilog/VHDL Silicon Solution
-Abundant, high-speed interconnect eliminates manual routing
-Flexible logic cell provides high efficiency
and
performance
-Design tools produce fast, efficient Verilog/VHDL synthesis
Speed, Density, Low Cost and Flexibility in One Device
-16-bit counter speeds exceeding 200 MHz
-9,000 usable ASIC gates, 16,000 usable PLD gates, 225 I/Os
-3-layer metal ViaLink
process for small die sizes
-100% routable and pin-out maintainable
Advanced Logic Cell and I/O Capabilities
-Complex functions (up to 16 inputs) in a single logic cell
-High synthesis gate utilization from logic cell fragments
-Full IEEE Standard JTAG boundary scan capability
-Individually-controlled input/feedback registers and OEs on all I/O pins
-3.3V and 5.0V operation with low standby power
-I/O pin-compatibility between different devices in the same packages
-PCI compliant (at 5.0V), full speed 33 MHz implementations
-High design security provided by security fuses
Other Important Family Features
… 9,000
usable ASIC gates,
225 I/O pins
672
Logic
Cells
p
3
QL2009
Block Diagram
Rev. C
pASIC 2
HIGHLIGHTS
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| QL2009-XPQ208I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:3.3V and 5.0V pASIC? 2 FPGA Combining Speed, Density, Low Cost and Flexibility |
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