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參數(shù)資料
| 型號： | QL5432-33APB456I |
| 英文描述： | ASIC |
| 中文描述： | 專用集成電路 |
| 文件頁數(shù)： | 1/20頁 |
| 文件大小： | 559K |
| 代理商： | QL5432-33APB456I |
33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM
last updated 2/5/01
QL5432 - Enhanced QuickPCI
TM
Device
Rev A
I
Supports all PCI commands (including configuration
and MWI)
I
Supports fully-customizable byte enables as a master
I
Zero-wait-state write and one-wait-state read target
interface
I
Supports all types of PCI target terminations: disconnect
with data transfer, disconnect without data transfer,
and retry
I
Supports target aborts
I
Has 125 more logic cells in FPGA section, but 2 less
RAM blocks
I
Pin Compatible with QL5232
High Performance PCI Controller
I
32-bit / 33 MHz PCI Master/Target
I
Zero-wait state PCI Master provides 132 MB/s
transfer rates
I
Zero-wait-state PCI Target Write/One-wait-state PCI
Target Read interface
I
Supports all PCI commands, including configuration
and MWI
I
Supports fully-customizable byte enable for master
channels
I
Target interface supports retry, disconnect with/without
data transfer, and target abort
I
Programmable back-end interface to optional local
processor
I
Independent PCI bus (33 MHz) and local bus
(up to 160 MHz) clocks
I
Fully customizable PCI Configuration Space
I
Configurable FIFOs with depths up to 256
I
Reference design with driver code (Win 95/98/
Win 2000/NT4.0) available
I
PCI v2.2 compliant
I
Supports Type 0 Configuration Cycles in Target mode
I
3.3V, 5V Tolerant PCI signaling supports Universal
PCI Adapter designs
I
3.3V CMOS in 208-pin PQFP and 456-pin PBGA
I
Supports endian conversions
I
Unlimited/Continuous Burst Transfers supported
FIGURE 1. QL5432 Diagram
Extendable PCI Functionality
I
Support for PCI host-bridge function
I
Support for Configuration Space from 0x40 to 0x3FF
I
Multi-Function, Expanded Capabilities, & Expansion
ROM capable
I
Power management, Compact PCI, hot-swap/
hot-plug compatible
I
PCI v2.2 Power Management Spec compatible
I
PCI v2.2 Vital Product Data (VPD) configuration support
I
Programmable Interrupt Generator
I
I
2
O support with local processor
I
Mailbox register support
Programmable Logic
I
1427 Logic Cells
I
23,040 RAM bits, up to 266 I/O pins
I
250 MHz 16-bit counters, 275 MHz Datapaths, 160
MHz FIFOs
I
All back-end interface and glue-logic can be implemented
on chip
I
Any combination of FIFOs that require 20 or less
QuickLogic RAM Modules
I
Six 32-bit busses interface between the PCI Controller
and the Programmable Logic
QL5432 - Enhanced QL5232
Device Highlights
Config
Space
160
MHz
FIFOs
MASTER
CONTROLLER
INTERFACE
PROGRAMMABLE LOGIC
32
PCI Bus – 33 MHz 32 bits (data and address)
266 User I/O
PCI CONTROLLER
DMA
Controller
HIGH
SPEED
DATA
PATH
High Speed
Logic Cells
TARGET
CONTROLLER
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