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參數(shù)資料
| 型號： | QL6500PS672 |
| 英文描述： | ASIC |
| 中文描述： | 專用集成電路 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大小： | 165K |
| 代理商： | QL6500PS672 |
Eclipse
TM
Family Data Sheet
1
Eclipse Family Data Sheet
Combining Performance, Density and Embedded RAM
1.0 Device Highlights
Flexible Programmable Logic
.25u, 5 layer metal CMOS process
2.5 V Vcc, 2.5/3.3 V drive capable I/O
Up to 4032 SuperCells
Up to 583,000 Max System Gates
Up to 512 I/O
Embedded Dual Port SRAM
Up to 36-2,304 bit Dual Port High
performance SRAM Blocks
Up to 82,900 RAM bits
RAM/ROM/FIFO Wizard for automatic
configuration
Configurable and Cascadable
Applications
Signal processing operators
Signal processing functions
Networking / communications for VoIP
Speech / voice processing
Channel coding
Programmable I/O
High performance Enhanced I/O (EIO):
Less than 3 ns Tco
Programmable Slew Rate Control
Programmable I/O Standards
LVTTL, LVCMOS, PCI, GTL+, SSTL2,
and SSTL3
8 Independent I/O Banks
3 Register Configuration: Input, Output, OE
Advanced Clock Network
9 Global Clock Networks
1 dedicated
8 programmable
16 I/O (high drive) Networks:
2 I/O’s per bank
20 Quad-Net Networks: 5 per quadrant
Figure 1: Embedded Eclipse Block Diagram
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