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參數資料
| 型號： | QS5931Q |
| 英文描述： | SIX DISTRIBUTED-OUTPUT CLOCK DRIVER|CMOS|SSOP|20PIN|PLASTIC |
| 中文描述： | 六分布式輸出時鐘驅動器|的CMOS | SSOP封裝| 20針|塑料 |
| 文件頁數： | 1/6頁 |
| 文件大小： | 92K |
| 代理商： | QS5931Q |
1
INDUSTRIAL TEMPERATURE RANGE
QS5935
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
FEEDBACK
CLK_IN
OE/RST
PLL_EN
PLL
Q
0
Q
1
Q
2
Q
3
Q
4
0
1
/2
JULY 2000
2000 Integrated Device Technology, Inc.
DSC-5816/-
c
QS5935
INDUSTRIAL TEMPERATURE RANGE
LOW SKEW CMOS PLL
CLOCK DRIVER WITH
INTEGRATED LOOP FILTER
FUNCTIONAL BLOCK DIAGRAM
FEATURES:
5V operation
Five low noise CMOS level outputs
<500ps output skew, Q
0
–Q
4
Outputs 3-state and reset while OE/
RST
low
PLL disable feature for low frequency testing
Internal loop filter RC network
Balanced drive outputs ±36mA
80MHz maximumfrequency
Available in QSOP package
DESCRIPTION
The QS5935 Clock Driver uses an internal phase locked loop (PLL)
to lock low skew outputs to a reference clock input. Five outputs are
available: Q
0
–Q
4
. Careful layout and design ensure <500ps skew between
the Q
0
–Q
4
. The QS5935 includes an internal RC filter which provides
excellent jitter characteristics and elimnates the need for external compo-
nents. The PLL can also be disabled by the PLL_EN signal to allow low
frequency or DC testing. The QS5935 is designed for use in cost sensitive
high-performance computing systems, workstations, multi-board comput-
ers, networking hardware, and mainframe systems. Several can be used
in parallel or scattered throughout a systemfor guaranteed low skew,
system-wide clock distribution networks. In the QSOP package, the QS5935
clock driver represents the best value in small formfactor, high-performance
clock management products.
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