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參數資料
| 型號： | QS5LV931-50Q |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| 中文描述： | 5LV SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封裝： | QSOP-20 |
| 文件頁數： | 1/8頁 |
| 文件大小： | 62K |
| 代理商： | QS5LV931-50Q |
1
INDUSTRIAL TEMPERATURE RANGE
QS5LV931
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
J ANUARY 2002
2002 Integrated Device Technology, Inc.
DSC-5821/2
c
INDUS T RIAL T E MPE RAT URE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FUNCTIONAL BLOCK DIAGRAM
QS5LV931
3.3V LOW SKEW CMOS PLL
CLOCK DRIVER WITH
INTEGRATED LOOP FILTER
DESCRIPTION:
The QS5LV931 Clock Driver uses an internal phase locked loop
(PLL) to lock low skew outputs to a reference clock input. Six outputs
are available: Q
0
–Q
4
, Q/2. Careful layout and design ensure <300ps
skew between the Q
0
–Q
4
, and Q/2 outputs. The QS5LV931 includes
an internal RC filter which provides excellent jitter characteristics and
elimnates the need for external components. Various combinations of
feedback and a divide-by-2 in the VCO path allow applications to be
customzed for linear VCO operation over a wide range of input SYNC
frequencies. The PLL can also be disabled by the PLL_EN signal to
allow low frequency or DC testing. The QS5LV931 is designed for use
in cost sensitive high-performance computing systems, workstations,
multi-board computers, networking hardware, and mainframe systems.
Several can be used in parallel or scattered throughout a systemfor
guaranteed low skew, system-wide clock distribution networks. In the
QSOP package, the QS5LV931 clock driver represents the best value
in small formfactor, high-performance clock management products.
For more information on PLL clock driver products, see Application
Note AN-227.
FEATURES:
3.3V operation
JEDEC LVTTL compatible level
Clock input is 5V tolerant
Q outputs, Q/2 output
<300ps output skew, Q
0
–Q
4
Outputs 3-state and reset while OE/
RST
low
PLL disable feature for low frequency testing
Internal loop filter RC network
Internal VCO/2 option
Balanced drive outputs ±24mA
ESD >2000V
80MHz maximum frequency
Available in QSOP package
R
D
Q
Q
0
R
D
Q
Q
1
R
D
Q
Q
2
R
D
Q
Q
3
R
D
Q
Q
4
R
D
Q
Q/
2
0
1
1
0
/2
VCO
LOOP
FILTER
PHASE
DETECTOR
FREQ_SEL
FEEDBACK
SYNC
PLL_EN
OE/RST
Q
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相關代理商/技術參數 |
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| QS5LV93166Q | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| QS5LV931-66Q | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| QS5LV93180Q | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| QS5LV931-80Q | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
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