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參數資料
| 型號： | R1LP0408CSC-7LI |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Wide Temperature Range Version 4 M SRAM (512-kword 】 8-bit) |
| 中文描述： | 寬溫版本四米的SRAM（512 - KWord的】8位） |
| 文件頁數： | 8/14頁 |
| 文件大小： | 78K |
| 代理商： | R1LP0408CSC-7LI |
R1LP0408C-I Series
Rev.1.00, Aug.01.2003, page 8 of 13
Write Cycle
R1LP0408C-I
-5
-7
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Write cycle time
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
t
OHZ
55
20
20
70
25
25
ns
Chip selection to end of write
50
60
ns
4
Address setup time
0
0
ns
5
Address valid to end of write
50
60
ns
Write pulse width
40
50
ns
3, 12
Write recovery time
0
0
ns
6
Write to output in high-Z
0
0
ns
1, 2, 7
Data to write time overlap
25
30
ns
Data hold from write time
0
0
ns
Output active from end of write
5
5
ns
2
Output disable to output in high-Z
Notes: 1. t
, t
and t
are defined as the time at which the outputs achieve the open circuit conditions
and are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. A write occurs during the overlap (t
) of a low CS# and a low WE#. A write begins at the later
transition of CS# going low or WE# going low. A write ends at the earlier transition of CS# going
high or WE# going high. t
WP
is measured from the beginning of write to the end of write.
4. t
CW
is measured from CS# going low to the end of write.
5. t
AS
is measured from the address valid to the beginning of write.
6. t
WR
is measured from the earlier of WE# or CS# going high to the end of write cycle.
7. During this period, I/O pins are in the output state so that the input signals of the opposite phase
to the outputs must not be applied.
8. If the CS# low transition occurs simultaneously with the WE# low transition or after the WE#
transition, the output remain in a high impedance state.
9. Dout is the same phase of the write data of this write cycle.
10. Dout is the read data of next address.
11. If CS# is low during this period, I/O pins are in the output state. Therefore, the input signals of
the opposite phase to the outputs must not be applied to them.
12. In the write cycle with OE# low fixed, t
WP
must satisfy the following equation to avoid a problem
of data bus contention. t
WP
≥
t
DW
min + t
WHZ
max
0
0
ns
1, 2, 7
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相關代理商/技術參數 |
參數描述 |
|---|---|
| R1LP0408CSP5SC | 制造商:RENESAS 功能描述:Pb Free |
| R1LP0408CSP-5SC | 制造商:Renesas Electronics Corporation 功能描述:4M SRAM 制造商:Renesas Electronics 功能描述:512k~8 55ns 5V 32SOP Tube |
| R1LP0408CSP-5SC#B0 | 功能描述:IC SRAM 4MBIT 55NS 32SOP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:72 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 存儲容量:4.5M（256K x 18） 速度:133MHz 接口:并聯 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應商設備封裝:100-TQFP（14x20） 包裝:托盤 |
| R1LP0408CSP5SC#S0 | 制造商:Renesas Electronics Corporation 功能描述: |
| R1LP0408CSP-5SC#S0 | 功能描述:IC SRAM 4MBIT 55NS 32SOP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1 系列:- 格式 - 存儲器:RAM 存儲器類型:SDRAM 存儲容量:256M（8Mx32） 速度:143MHz 接口:并聯 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應商設備封裝:90-VFBGA（8x13） 包裝:托盤 其它名稱:Q2841869 |
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