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參數資料
| 型號： | R5F2138AFJFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | FLASH, 20 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件頁數： | 1/30頁 |
| 文件大?。?/td> | 483K |
| 代理商： | R5F2138AFJFP |
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59
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
Bit 5 – PCIE1: Pin Change Interrupt Enable 1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 1 is
enabled. Any change on any enabled PCINT15...8 pin will cause an interrupt. The corresponding interrupt of Pin
Change Interrupt Request is executed from the PCI1 Interrupt Vector. PCINT15:8 pins are enabled individually by
the PCMSK1 Register.
Bit 4 – PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is
enabled. Any change on any enabled PCINT7...0 pin will cause an interrupt. The corresponding interrupt of Pin
Change Interrupt Request is executed from the PCI0 Interrupt Vector. PCINT7:0 pins are enabled individually by
the PCMSK0 Register.
Bit 0 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is
enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the External Interrupt Control Register A
(EICRA) define whether the external interrupt is activated on rising and/or falling edge of the INT0 pin or level
sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The correspond-
ing interrupt of External Interrupt Request 0 is executed from the INT0 Interrupt Vector.
13.2.3
EIFR – External Interrupt Flag Register
Bit 7 – PCIF3: Pin Change Interrupt Flag 3
When a logic change on any PCINT30:24 pin triggers an interrupt request, PCIF3 becomes set (one). If the I-bit in
SREG and the PCIE3 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag
is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
Note:
1. This bit is a reserved bit in Atmel
ATmega165A/ATmega165PA/ATmega325A/ATmega325PA/ATmega645A/ATmega645P and should always be writ-
ten to zero.
Bit 6 – PCIF2: Pin Change Interrupt Flag 2
When a logic change on any PCINT24:16 pin triggers an interrupt request, PCIF2 becomes set (one). If the I-bit in
SREG and the PCIE2 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag
is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
Note:
1. This bit is a reserved bit in Atmel
ATmega165A/ATmega165PA/ATmega325A/ATmega325PA/ATmega645A/ATmega645P and should always be writ-
ten to zero.
Bit 5 – PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT15:8 pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in
SREG and the PCIE1 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag
is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
Bit 4 – PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT7:0 pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in
SREG and the PCIE0 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag
is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
Bit
76543210
0x1C (0x3C)
PCIF3
PCIF2
PCIF1
PCIF0
–
INTF0
EIFR
Read/Write
R/W
RRR
R/W
Initial Value
00000000
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