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參數資料
| 型號： | RC32365T365-150BCG |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | IDTTM InterpriseTM Integrated Communications Processor |
| 中文描述： | IDTTM InterpriseTM集成通信處理器 |
| 文件頁數： | 1/44頁 |
| 文件大小： | 341K |
| 代理商： | RC32365T365-150BCG |
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October 5, 2005
2005 Integrated Device Technology, Inc.
DSC 6210
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
Devic e Overview
The RC32365 device is a member of the IDT Interprise famly of
integrated communications processors. This device is designed to
address a range of communications applications that require the effi-
cient processing of IPSec algorithms. These applications include gate-
ways, wireless access points, and virtual private network (VPN)
equipment. The key to the RC32365’s efficient processing of IPSec
algorithms is a highly progammable security engine which off-loads the
CPU core of encryption/decryption, hashing, and padding tasks.
Features List
◆
RC32300 32-bit CPU core
–
32-bit MIPS instruction set
–
Supports big or little endian operation
–
MMU
–
16-entry TLB
–
Supports variable page sizes and enhanced write algo-
rithm
–
Supports variable number of locked entries
–
8KB Instruction Cache
–
2-way set associative
–
LRU replacement algorithm
–
4 word line size
–
Sub-block ordering
–
Word parity
–
Per line cache locking
–
2KB Data Cache
–
–
–
–
–
–
–
2-way set associative
LRU replacement algorithm
4 word line size
Sub-block ordering
Byte parity
Per line cache locking
Can be programmed on a page basis to implement write-
through no write allocate, write-through write allocate, or
write-back algorithms
Enhanced EJTAG and JTAG Interfaces
–
Compatible with IEEE Std. 1149.1-1990
◆
Security Engine
–
Dedicated DMA channels for high speed data transfers to and
fromthe security engine
–
On-chip memory for storage of two security contexts
–
Supports ECB and CBC modes for the following symmetric
encryption algorithms: DES, triple DES (both two key (k1=k3)
and three key (k1!=k3) modes), AES-128 with 128-bit blocks,
AES-192 with 128-bit blocks
–
Hardware support for encryption pad generation and checking
using one of seven popular padding algorithms: supports pad
algorithmrequired by IPSec ESP
–
Supports MD5 and SHA-1 one-way hash functions
–
Programmable truncation length of computed hash and HMAC
on a security context basis
–
Supports concurrent hash and encryption operations
–
Block Diagram
Figure 1 RC32365 Internal Block Diagram
EJTAG
MMU
D. Cache
I. Cache
32-bit MIPS
CPU Core
JTAG
Interrupt
Controller
3 Counter
Timers
Bus/System
Integrity
Monitor
DMA
Controller
Arbiter
SDRAM & Device
Controllers
including PCMCIA
Support
UART
(16550)
GPIO
Interface
PCI
Master/Target
Interface
Memory &
Peripheral Bus
(including PCMCIA)
Serial Channel
GPIO Pins
PCI Bus
Controller
SPI
SPI Bus
MII
MII
IPBus
TM
PCI Arbiter
(Host Mode)
.
.
Security Functions
Security
Context Storage
RNG
Encryption
Unit
Unit
Hash
10/100
Interfaces
2 Ethernet
RC32365
IDT
TM
Interprise
TM
Integrated
Communications Processor
相關PDF資料 |
PDF描述 |
|---|---|
| RC32365T365-150BCGI | IDTTM InterpriseTM Integrated Communications Processor |
| RC32365T365-150BCI | IDTTM InterpriseTM Integrated Communications Processor |
| RC32434 | IDT TInterprise Integrated Communications Processor |
| RC32434-266BC | IDT TInterprise Integrated Communications Processor |
| RC32434-266BCI | IDT TInterprise Integrated Communications Processor |
相關代理商/技術參數 |
參數描述 |
|---|---|
| RC32365T365-150BCGI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:IDTTM InterpriseTM Integrated Communications Processor |
| RC32365T365-150BCI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:IDTTM InterpriseTM Integrated Communications Processor |
| RC32434 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:IDT TInterprise Integrated Communications Processor |
| RC32434-266BC | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:IDT TInterprise Integrated Communications Processor |
| RC32434-266BCI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:IDT TInterprise Integrated Communications Processor |
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